at32f423_tmr.c 56 KB

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  1. /**
  2. **************************************************************************
  3. * @file at32f423_tmr.c
  4. * @brief contains all the functions for the tmr firmware library
  5. **************************************************************************
  6. * Copyright notice & Disclaimer
  7. *
  8. * The software Board Support Package (BSP) that is made available to
  9. * download from Artery official website is the copyrighted work of Artery.
  10. * Artery authorizes customers to use, copy, and distribute the BSP
  11. * software and its related documentation for the purpose of design and
  12. * development in conjunction with Artery microcontrollers. Use of the
  13. * software is governed by this copyright notice and the following disclaimer.
  14. *
  15. * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
  16. * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
  17. * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
  18. * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
  19. * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
  21. *
  22. **************************************************************************
  23. */
  24. #include "at32f423_conf.h"
  25. /** @addtogroup AT32F423_periph_driver
  26. * @{
  27. */
  28. /** @defgroup TMR
  29. * @brief TMR driver modules
  30. * @{
  31. */
  32. #ifdef TMR_MODULE_ENABLED
  33. /** @defgroup TMR_private_functions
  34. * @{
  35. */
  36. /**
  37. * @brief tmr reset by crm reset register
  38. * @param tmr_x: select the tmr peripheral.
  39. * this parameter can be one of the following values:
  40. * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7,
  41. * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  42. * @retval none
  43. */
  44. void tmr_reset(tmr_type *tmr_x)
  45. {
  46. if(tmr_x == TMR1)
  47. {
  48. crm_periph_reset(CRM_TMR1_PERIPH_RESET, TRUE);
  49. crm_periph_reset(CRM_TMR1_PERIPH_RESET, FALSE);
  50. }
  51. else if(tmr_x == TMR2)
  52. {
  53. crm_periph_reset(CRM_TMR2_PERIPH_RESET, TRUE);
  54. crm_periph_reset(CRM_TMR2_PERIPH_RESET, FALSE);
  55. }
  56. else if(tmr_x == TMR3)
  57. {
  58. crm_periph_reset(CRM_TMR3_PERIPH_RESET, TRUE);
  59. crm_periph_reset(CRM_TMR3_PERIPH_RESET, FALSE);
  60. }
  61. else if(tmr_x == TMR4)
  62. {
  63. crm_periph_reset(CRM_TMR4_PERIPH_RESET, TRUE);
  64. crm_periph_reset(CRM_TMR4_PERIPH_RESET, FALSE);
  65. }
  66. else if(tmr_x == TMR6)
  67. {
  68. crm_periph_reset(CRM_TMR6_PERIPH_RESET, TRUE);
  69. crm_periph_reset(CRM_TMR6_PERIPH_RESET, FALSE);
  70. }
  71. else if(tmr_x == TMR7)
  72. {
  73. crm_periph_reset(CRM_TMR7_PERIPH_RESET, TRUE);
  74. crm_periph_reset(CRM_TMR7_PERIPH_RESET, FALSE);
  75. }
  76. else if(tmr_x == TMR9)
  77. {
  78. crm_periph_reset(CRM_TMR9_PERIPH_RESET, TRUE);
  79. crm_periph_reset(CRM_TMR9_PERIPH_RESET, FALSE);
  80. }
  81. else if(tmr_x == TMR10)
  82. {
  83. crm_periph_reset(CRM_TMR10_PERIPH_RESET, TRUE);
  84. crm_periph_reset(CRM_TMR10_PERIPH_RESET, FALSE);
  85. }
  86. else if(tmr_x == TMR11)
  87. {
  88. crm_periph_reset(CRM_TMR11_PERIPH_RESET, TRUE);
  89. crm_periph_reset(CRM_TMR11_PERIPH_RESET, FALSE);
  90. }
  91. else if(tmr_x == TMR12)
  92. {
  93. crm_periph_reset(CRM_TMR12_PERIPH_RESET, TRUE);
  94. crm_periph_reset(CRM_TMR12_PERIPH_RESET, FALSE);
  95. }
  96. else if(tmr_x == TMR13)
  97. {
  98. crm_periph_reset(CRM_TMR13_PERIPH_RESET, TRUE);
  99. crm_periph_reset(CRM_TMR13_PERIPH_RESET, FALSE);
  100. }
  101. else if(tmr_x == TMR14)
  102. {
  103. crm_periph_reset(CRM_TMR14_PERIPH_RESET, TRUE);
  104. crm_periph_reset(CRM_TMR14_PERIPH_RESET, FALSE);
  105. }
  106. }
  107. /**
  108. * @brief enable or disable tmr counter
  109. * @param tmr_x: select the tmr peripheral.
  110. * this parameter can be one of the following values:
  111. * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7,
  112. * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  113. * @param new_state (TRUE or FALSE)
  114. * @retval none
  115. */
  116. void tmr_counter_enable(tmr_type *tmr_x, confirm_state new_state)
  117. {
  118. /* tmr counter enable */
  119. tmr_x->ctrl1_bit.tmren = new_state;
  120. }
  121. /**
  122. * @brief init tmr output default para
  123. * @param tmr_output_struct
  124. * - to the structure of tmr_output_config_type
  125. * @retval none
  126. */
  127. void tmr_output_default_para_init(tmr_output_config_type *tmr_output_struct)
  128. {
  129. tmr_output_struct->oc_mode = TMR_OUTPUT_CONTROL_OFF;
  130. tmr_output_struct->oc_idle_state = FALSE;
  131. tmr_output_struct->occ_idle_state = FALSE;
  132. tmr_output_struct->oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
  133. tmr_output_struct->occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
  134. tmr_output_struct->oc_output_state = FALSE;
  135. tmr_output_struct->occ_output_state = FALSE;
  136. }
  137. /**
  138. * @brief init tmr input default para
  139. * @param tmr_input_struct
  140. * - to the structure of tmr_input_config_type
  141. * @retval none
  142. */
  143. void tmr_input_default_para_init(tmr_input_config_type *tmr_input_struct)
  144. {
  145. tmr_input_struct->input_channel_select = TMR_SELECT_CHANNEL_1;
  146. tmr_input_struct->input_polarity_select = TMR_INPUT_RISING_EDGE;
  147. tmr_input_struct->input_mapped_select = TMR_CC_CHANNEL_MAPPED_DIRECT;
  148. tmr_input_struct->input_filter_value = 0x0;
  149. }
  150. /**
  151. * @brief init tmr brkdt default para
  152. * @param tmr_brkdt_struct
  153. * - to the structure of tmr_brkdt_config_type
  154. * @retval none
  155. */
  156. void tmr_brkdt_default_para_init(tmr_brkdt_config_type *tmr_brkdt_struct)
  157. {
  158. tmr_brkdt_struct->deadtime = 0x0;
  159. tmr_brkdt_struct->brk_polarity = TMR_BRK_INPUT_ACTIVE_LOW;
  160. tmr_brkdt_struct->wp_level = TMR_WP_OFF;
  161. tmr_brkdt_struct->auto_output_enable = FALSE ;
  162. tmr_brkdt_struct->fcsoen_state = FALSE ;
  163. tmr_brkdt_struct->fcsodis_state = FALSE ;
  164. tmr_brkdt_struct->brk_enable = FALSE ;
  165. }
  166. /**
  167. * @brief init tmr base
  168. * @param tmr_x: select the tmr peripheral.
  169. * this parameter can be one of the following values:
  170. * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7,
  171. * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  172. * @param tmr_pr (for 16 bit tmr 0x0000~0xFFFF,
  173. * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF)
  174. * @param tmr_div (timer div value:0x0000~0xFFFF)
  175. * @retval none
  176. */
  177. void tmr_base_init(tmr_type* tmr_x, uint32_t tmr_pr, uint32_t tmr_div)
  178. {
  179. /* set the pr value */
  180. tmr_x->pr = tmr_pr;
  181. /* set the div value */
  182. tmr_x->div = tmr_div;
  183. /* trigger the overflow event to immediately reload pr value and div value */
  184. tmr_x->swevt_bit.ovfswtr = TRUE;
  185. }
  186. /**
  187. * @brief set tmr clock source division
  188. * @param tmr_x: select the tmr peripheral.
  189. * this parameter can be one of the following values:
  190. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR10,
  191. * TMR11, TMR12, TMR13, TMR14
  192. * @param tmr_clock_div
  193. * this parameter can be one of the following values:
  194. * - TMR_CLOCK_DIV1
  195. * - TMR_CLOCK_DIV2
  196. * - TMR_CLOCK_DIV4
  197. * @retval none
  198. */
  199. void tmr_clock_source_div_set(tmr_type *tmr_x, tmr_clock_division_type tmr_clock_div)
  200. {
  201. /* set tmr clock source division */
  202. tmr_x->ctrl1_bit.clkdiv = tmr_clock_div;
  203. }
  204. /**
  205. * @brief set tmr counter count direction
  206. * @param tmr_x: select the tmr peripheral.
  207. * this parameter can be one of the following values:
  208. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR10,
  209. * TMR11, TMR12, TMR13, TMR14
  210. * @param tmr_cnt_dir
  211. * this parameter can be one of the following values:
  212. * - TMR_COUNT_UP
  213. * - TMR_COUNT_DOWN
  214. * - TMR_COUNT_TWO_WAY_1
  215. * - TMR_COUNT_TWO_WAY_2
  216. * - TMR_COUNT_TWO_WAY_3
  217. * @retval none
  218. */
  219. void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir)
  220. {
  221. /* set the cnt direct */
  222. tmr_x->ctrl1_bit.cnt_dir = tmr_cnt_dir;
  223. }
  224. /**
  225. * @brief set the repetition counter register(rpr) value
  226. * @param tmr_x: select the tmr peripheral.
  227. * this parameter can be one of the following values:
  228. * TMR1, TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  229. * @param tmr_rpr_value (0x0000~0xFFFF)
  230. * @retval none
  231. */
  232. void tmr_repetition_counter_set(tmr_type *tmr_x, uint16_t tmr_rpr_value)
  233. {
  234. /* set the repetition counter value */
  235. tmr_x->rpr_bit.rpr = tmr_rpr_value;
  236. }
  237. /**
  238. * @brief set tmr counter value
  239. * @param tmr_x: select the tmr peripheral.
  240. * this parameter can be one of the following values:
  241. * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7,
  242. * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  243. * @param tmr_cnt_value (for 16 bit tmr 0x0000~0xFFFF,
  244. * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF)
  245. * @retval none
  246. */
  247. void tmr_counter_value_set(tmr_type *tmr_x, uint32_t tmr_cnt_value)
  248. {
  249. /* set the tmr counter value */
  250. tmr_x->cval = tmr_cnt_value;
  251. }
  252. /**
  253. * @brief get tmr counter value
  254. * @param tmr_x: select the tmr peripheral.
  255. * this parameter can be one of the following values:
  256. * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7,
  257. * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  258. * @retval tmr counter value
  259. */
  260. uint32_t tmr_counter_value_get(tmr_type *tmr_x)
  261. {
  262. return tmr_x->cval;
  263. }
  264. /**
  265. * @brief set tmr div value
  266. * @param tmr_x: select the tmr peripheral.
  267. * this parameter can be one of the following values:
  268. * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7,
  269. * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  270. * @param tmr_div_value (for 16 bit tmr 0x0000~0xFFFF,
  271. * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF)
  272. * @retval none
  273. */
  274. void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value)
  275. {
  276. /* set the tmr div value */
  277. tmr_x->div = tmr_div_value;
  278. }
  279. /**
  280. * @brief get tmr div value
  281. * @param tmr_x: select the tmr peripheral.
  282. * this parameter can be one of the following values:
  283. * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7,
  284. * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  285. * @retval tmr div value
  286. */
  287. uint32_t tmr_div_value_get(tmr_type *tmr_x)
  288. {
  289. return tmr_x->div;
  290. }
  291. /**
  292. * @brief config tmr output channel
  293. * @param tmr_x: select the tmr peripheral.
  294. * this parameter can be one of the following values:
  295. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR10,
  296. * TMR11, TMR12, TMR13, TMR14
  297. * @param tmr_channel
  298. * this parameter can be one of the following values:
  299. * - TMR_SELECT_CHANNEL_1
  300. * - TMR_SELECT_CHANNEL_2
  301. * - TMR_SELECT_CHANNEL_3
  302. * - TMR_SELECT_CHANNEL_4
  303. * - TMR_SELECT_CHANNEL_5
  304. * @param tmr_output_struct
  305. * - to the structure of tmr_output_config_type
  306. * @retval none
  307. */
  308. void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
  309. tmr_output_config_type *tmr_output_struct)
  310. {
  311. uint16_t channel_index = 0, channel_c_index = 0, channel = 0, chx_offset, chcx_offset;
  312. chx_offset = (8 + tmr_channel);
  313. chcx_offset = (9 + tmr_channel);
  314. /* get channel idle state bit position in ctrl2 register */
  315. channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << chx_offset);
  316. /* get channel complementary idle state bit position in ctrl2 register */
  317. channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << chcx_offset);
  318. /* set output channel complementary idle state */
  319. tmr_x->ctrl2 &= ~(1<<chcx_offset);
  320. tmr_x->ctrl2 |= channel_c_index;
  321. /* set output channel idle state */
  322. tmr_x->ctrl2 &= ~(1<<chx_offset);
  323. tmr_x->ctrl2 |= channel_index;
  324. /* set channel output mode */
  325. channel = tmr_channel;
  326. switch(channel)
  327. {
  328. case TMR_SELECT_CHANNEL_1:
  329. tmr_x->cm1_output_bit.c1octrl = tmr_output_struct->oc_mode;
  330. break;
  331. case TMR_SELECT_CHANNEL_2:
  332. tmr_x->cm1_output_bit.c2octrl = tmr_output_struct->oc_mode;
  333. break;
  334. case TMR_SELECT_CHANNEL_3:
  335. tmr_x->cm2_output_bit.c3octrl = tmr_output_struct->oc_mode;
  336. break;
  337. case TMR_SELECT_CHANNEL_4:
  338. tmr_x->cm2_output_bit.c4octrl = tmr_output_struct->oc_mode;
  339. break;
  340. case TMR_SELECT_CHANNEL_5:
  341. tmr_x->cm3_output_bit.c5octrl = tmr_output_struct->oc_mode;
  342. break;
  343. default:
  344. break;
  345. }
  346. chx_offset = ((tmr_channel * 2) + 1);
  347. chcx_offset = ((tmr_channel * 2) + 3);
  348. /* get channel polarity bit position in cctrl register */
  349. channel_index = (uint16_t)(tmr_output_struct->oc_polarity << chx_offset);
  350. /* get channel complementary polarity bit position in cctrl register */
  351. channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << chcx_offset);
  352. /* set output channel complementary polarity */
  353. tmr_x->cctrl &= ~(1<<chcx_offset);
  354. tmr_x->cctrl |= channel_c_index;
  355. /* set output channel polarity */
  356. tmr_x->cctrl &= ~(1<<chx_offset);
  357. tmr_x->cctrl |= channel_index;
  358. chx_offset = (tmr_channel * 2);
  359. chcx_offset = ((tmr_channel * 2) + 2);
  360. /* get channel enable bit position in cctrl register */
  361. channel_index = (uint16_t)(tmr_output_struct->oc_output_state << (tmr_channel * 2));
  362. /* get channel complementary enable bit position in cctrl register */
  363. channel_c_index = (uint16_t)(tmr_output_struct->occ_output_state << ((tmr_channel * 2) + 2));
  364. /* set output channel complementary enable bit */
  365. tmr_x->cctrl &= ~(1<<chcx_offset);
  366. tmr_x->cctrl |= channel_c_index;
  367. /* set output channel enable bit */
  368. tmr_x->cctrl &= ~(1<<chx_offset);
  369. tmr_x->cctrl |= channel_index;
  370. }
  371. /**
  372. * @brief select tmr output channel mode
  373. * @param tmr_x: select the tmr peripheral.
  374. * this parameter can be one of the following values:
  375. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR10,
  376. * TMR11, TMR12, TMR13, TMR14
  377. * @param tmr_channel
  378. * this parameter can be one of the following values:
  379. * - TMR_SELECT_CHANNEL_1
  380. * - TMR_SELECT_CHANNEL_2
  381. * - TMR_SELECT_CHANNEL_3
  382. * - TMR_SELECT_CHANNEL_4
  383. * - TMR_SELECT_CHANNEL_5
  384. * @param oc_mode
  385. * this parameter can be one of the following values:
  386. * - TMR_OUTPUT_CONTROL_OFF
  387. * - TMR_OUTPUT_CONTROL_HIGH
  388. * - TMR_OUTPUT_CONTROL_LOW
  389. * - TMR_OUTPUT_CONTROL_SWITCH
  390. * - TMR_OUTPUT_CONTROL_FORCE_HIGH
  391. * - TMR_OUTPUT_CONTROL_FORCE_LOW
  392. * - TMR_OUTPUT_CONTROL_PWM_MODE_A
  393. * - TMR_OUTPUT_CONTROL_PWM_MODE_B
  394. * @retval none
  395. */
  396. void tmr_output_channel_mode_select(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
  397. tmr_output_control_mode_type oc_mode)
  398. {
  399. uint16_t channel;
  400. channel = tmr_channel;
  401. switch(channel)
  402. {
  403. case TMR_SELECT_CHANNEL_1:
  404. tmr_x->cm1_output_bit.c1octrl = oc_mode;
  405. break;
  406. case TMR_SELECT_CHANNEL_2:
  407. tmr_x->cm1_output_bit.c2octrl = oc_mode;
  408. break;
  409. case TMR_SELECT_CHANNEL_3:
  410. tmr_x->cm2_output_bit.c3octrl = oc_mode;
  411. break;
  412. case TMR_SELECT_CHANNEL_4:
  413. tmr_x->cm2_output_bit.c4octrl = oc_mode;
  414. break;
  415. case TMR_SELECT_CHANNEL_5:
  416. tmr_x->cm3_output_bit.c5octrl = oc_mode;
  417. break;
  418. default:
  419. break;
  420. }
  421. }
  422. /**
  423. * @brief set tmr period value
  424. * @param tmr_x: select the tmr peripheral.
  425. * this parameter can be one of the following values:
  426. * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7,
  427. * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  428. * @param tmr_pr_value: timer period register value of counter
  429. * (for 16 bit tmr 0x0000~0xFFFF,
  430. * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF)
  431. * @retval none
  432. */
  433. void tmr_period_value_set(tmr_type *tmr_x, uint32_t tmr_pr_value)
  434. {
  435. /* set tmr period value */
  436. tmr_x->pr = tmr_pr_value;
  437. }
  438. /**
  439. * @brief get tmr period value
  440. * @param tmr_x: select the tmr peripheral.
  441. * this parameter can be one of the following values:
  442. * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7,
  443. * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  444. * @retval timer period register value of counter
  445. * (for 16 bit tmr 0x0000~0xFFFF, for 32 bit tmr
  446. * 0x0000_0000~0xFFFF_FFFF)
  447. */
  448. uint32_t tmr_period_value_get(tmr_type *tmr_x)
  449. {
  450. return tmr_x->pr;
  451. }
  452. /**
  453. * @brief set tmr channel value
  454. * @param tmr_x: select the tmr peripheral.
  455. * this parameter can be one of the following values:
  456. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR10,
  457. * TMR11, TMR12, TMR13, TMR14
  458. * @param tmr_channel
  459. * this parameter can be one of the following values:
  460. * - TMR_SELECT_CHANNEL_1
  461. * - TMR_SELECT_CHANNEL_2
  462. * - TMR_SELECT_CHANNEL_3
  463. * - TMR_SELECT_CHANNEL_4
  464. * - TMR_SELECT_CHANNEL_5
  465. * @param tmr_channel_value (for 16 bit tmr 0x0000~0xFFFF,
  466. * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF)
  467. * @retval none
  468. */
  469. void tmr_channel_value_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
  470. uint32_t tmr_channel_value)
  471. {
  472. uint16_t channel;
  473. channel = tmr_channel;
  474. /* set tmr channel value */
  475. switch(channel)
  476. {
  477. case TMR_SELECT_CHANNEL_1:
  478. tmr_x->c1dt = tmr_channel_value;
  479. break;
  480. case TMR_SELECT_CHANNEL_2:
  481. tmr_x->c2dt = tmr_channel_value;
  482. break;
  483. case TMR_SELECT_CHANNEL_3:
  484. tmr_x->c3dt = tmr_channel_value;
  485. break;
  486. case TMR_SELECT_CHANNEL_4:
  487. tmr_x->c4dt = tmr_channel_value;
  488. break;
  489. case TMR_SELECT_CHANNEL_5:
  490. tmr_x->c5dt = tmr_channel_value;
  491. break;
  492. default:
  493. break;
  494. }
  495. }
  496. /**
  497. * @brief get tmr channel value
  498. * @param tmr_x: select the tmr peripheral.
  499. * this parameter can be one of the following values:
  500. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR10,
  501. * TMR11, TMR12, TMR13, TMR14
  502. * @param tmr_channel
  503. * this parameter can be one of the following values:
  504. * - TMR_SELECT_CHANNEL_1
  505. * - TMR_SELECT_CHANNEL_2
  506. * - TMR_SELECT_CHANNEL_3
  507. * - TMR_SELECT_CHANNEL_4
  508. * - TMR_SELECT_CHANNEL_5
  509. * @retval tmr channel value
  510. */
  511. uint32_t tmr_channel_value_get(tmr_type *tmr_x, tmr_channel_select_type tmr_channel)
  512. {
  513. uint32_t cc_value_get = 0;
  514. uint16_t channel;
  515. channel = tmr_channel;
  516. /* get tmr channel value */
  517. switch(channel)
  518. {
  519. case TMR_SELECT_CHANNEL_1:
  520. cc_value_get = tmr_x->c1dt;
  521. break;
  522. case TMR_SELECT_CHANNEL_2:
  523. cc_value_get = tmr_x->c2dt;
  524. break;
  525. case TMR_SELECT_CHANNEL_3:
  526. cc_value_get = tmr_x->c3dt;
  527. break;
  528. case TMR_SELECT_CHANNEL_4:
  529. cc_value_get = tmr_x->c4dt;
  530. break;
  531. case TMR_SELECT_CHANNEL_5:
  532. cc_value_get = tmr_x->c5dt;
  533. break;
  534. default:
  535. break;
  536. }
  537. return cc_value_get;
  538. }
  539. /**
  540. * @brief set tmr period buffer
  541. * @param tmr_x: select the tmr peripheral.
  542. * this parameter can be one of the following values:
  543. * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7,
  544. * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  545. * @param new_state (TRUE or FALSE)
  546. * @retval none
  547. */
  548. void tmr_period_buffer_enable(tmr_type *tmr_x, confirm_state new_state)
  549. {
  550. /* tmr period buffer set */
  551. tmr_x->ctrl1_bit.prben = new_state;
  552. }
  553. /**
  554. * @brief set tmr output channel buffer
  555. * @param tmr_x: select the tmr peripheral.
  556. * this parameter can be one of the following values:
  557. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR10,
  558. * TMR11, TMR12, TMR13, TMR14
  559. * @param tmr_channel
  560. * this parameter can be one of the following values:
  561. * - TMR_SELECT_CHANNEL_1
  562. * - TMR_SELECT_CHANNEL_2
  563. * - TMR_SELECT_CHANNEL_3
  564. * - TMR_SELECT_CHANNEL_4
  565. * - TMR_SELECT_CHANNEL_5
  566. * @param new_state (TRUE or FALSE)
  567. * @retval none
  568. */
  569. void tmr_output_channel_buffer_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
  570. confirm_state new_state)
  571. {
  572. uint16_t channel;
  573. channel = tmr_channel;
  574. /* get tmr channel value */
  575. switch(channel)
  576. {
  577. case TMR_SELECT_CHANNEL_1:
  578. tmr_x->cm1_output_bit.c1oben = new_state;
  579. break;
  580. case TMR_SELECT_CHANNEL_2:
  581. tmr_x->cm1_output_bit.c2oben = new_state;
  582. break;
  583. case TMR_SELECT_CHANNEL_3:
  584. tmr_x->cm2_output_bit.c3oben = new_state;
  585. break;
  586. case TMR_SELECT_CHANNEL_4:
  587. tmr_x->cm2_output_bit.c4oben = new_state;
  588. break;
  589. case TMR_SELECT_CHANNEL_5:
  590. tmr_x->cm3_output_bit.c5oben = new_state;
  591. break;
  592. default:
  593. break;
  594. }
  595. }
  596. /**
  597. * @brief set tmr output channel immediately
  598. * @param tmr_x: select the tmr peripheral.
  599. * this parameter can be one of the following values:
  600. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR10,
  601. * TMR11, TMR12, TMR13, TMR14
  602. * @param tmr_channel
  603. * this parameter can be one of the following values:
  604. * - TMR_SELECT_CHANNEL_1
  605. * - TMR_SELECT_CHANNEL_2
  606. * - TMR_SELECT_CHANNEL_3
  607. * - TMR_SELECT_CHANNEL_4
  608. * - TMR_SELECT_CHANNEL_5
  609. * @param new_state (TRUE or FALSE)
  610. * @retval none
  611. */
  612. void tmr_output_channel_immediately_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
  613. confirm_state new_state)
  614. {
  615. uint16_t channel;
  616. channel = tmr_channel;
  617. /* get tmr channel value */
  618. switch(channel)
  619. {
  620. case TMR_SELECT_CHANNEL_1:
  621. tmr_x->cm1_output_bit.c1oien = new_state;
  622. break;
  623. case TMR_SELECT_CHANNEL_2:
  624. tmr_x->cm1_output_bit.c2oien = new_state;
  625. break;
  626. case TMR_SELECT_CHANNEL_3:
  627. tmr_x->cm2_output_bit.c3oien = new_state;
  628. break;
  629. case TMR_SELECT_CHANNEL_4:
  630. tmr_x->cm2_output_bit.c4oien = new_state;
  631. break;
  632. case TMR_SELECT_CHANNEL_5:
  633. tmr_x->cm3_output_bit.c5oien = new_state;
  634. break;
  635. default:
  636. break;
  637. }
  638. }
  639. /**
  640. * @brief set tmr output channel switch
  641. * @param tmr_x: select the tmr peripheral.
  642. * this parameter can be one of the following values:
  643. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR10,
  644. * TMR11, TMR12, TMR13, TMR14
  645. * @param tmr_channel
  646. * this parameter can be one of the following values:
  647. * - TMR_SELECT_CHANNEL_1
  648. * - TMR_SELECT_CHANNEL_2
  649. * - TMR_SELECT_CHANNEL_3
  650. * - TMR_SELECT_CHANNEL_4
  651. * - TMR_SELECT_CHANNEL_5
  652. * @param new_state (TRUE or FALSE)
  653. * @retval none
  654. */
  655. void tmr_output_channel_switch_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
  656. confirm_state new_state)
  657. {
  658. uint16_t channel;
  659. channel = tmr_channel;
  660. /* get tmr channel value */
  661. switch(channel)
  662. {
  663. case TMR_SELECT_CHANNEL_1:
  664. tmr_x->cm1_output_bit.c1osen = new_state;
  665. break;
  666. case TMR_SELECT_CHANNEL_2:
  667. tmr_x->cm1_output_bit.c2osen = new_state;
  668. break;
  669. case TMR_SELECT_CHANNEL_3:
  670. tmr_x->cm2_output_bit.c3osen = new_state;
  671. break;
  672. case TMR_SELECT_CHANNEL_4:
  673. tmr_x->cm2_output_bit.c4osen = new_state;
  674. break;
  675. case TMR_SELECT_CHANNEL_5:
  676. tmr_x->cm3_output_bit.c5osen = new_state;
  677. break;
  678. default:
  679. break;
  680. }
  681. }
  682. /**
  683. * @brief enable or disable tmr one cycle mode
  684. * @param tmr_x: select the tmr peripheral.
  685. * this parameter can be one of the following values:
  686. * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7,
  687. * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  688. * @param new_state (TRUE or FALSE)
  689. * @retval none
  690. */
  691. void tmr_one_cycle_mode_enable(tmr_type *tmr_x, confirm_state new_state)
  692. {
  693. /* tmr one cycle mode enable */
  694. tmr_x->ctrl1_bit.ocmen = new_state;
  695. }
  696. /**
  697. * @brief enable or disable tmr 32 bit function(plus mode)
  698. * @param tmr_x: select the tmr peripheral.
  699. * this parameter can be one of the following values:
  700. * TMR2
  701. * @param new_state (TRUE or FALSE)
  702. * @retval none
  703. */
  704. void tmr_32_bit_function_enable (tmr_type *tmr_x, confirm_state new_state)
  705. {
  706. /* tmr 32 bit function(plus mode) enable,only for TMR2/TMR5 */
  707. if(tmr_x == TMR2)
  708. {
  709. tmr_x->ctrl1_bit.pmen = new_state;
  710. }
  711. }
  712. /**
  713. * @brief select tmr the overflow event sources
  714. * @param tmr_x: select the tmr peripheral.
  715. * this parameter can be one of the following values:
  716. * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7,
  717. * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  718. * @param new_state (TRUE or FALSE)
  719. * @retval none
  720. */
  721. void tmr_overflow_request_source_set(tmr_type *tmr_x, confirm_state new_state)
  722. {
  723. tmr_x->ctrl1_bit.ovfs = new_state;
  724. }
  725. /**
  726. * @brief enable or disable tmr overflow event generation
  727. * @param tmr_x: select the tmr peripheral.
  728. * this parameter can be one of the following values:
  729. * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7,
  730. * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  731. * @param new_state (TRUE or FALSE)
  732. * @retval none
  733. */
  734. void tmr_overflow_event_disable(tmr_type *tmr_x, confirm_state new_state)
  735. {
  736. tmr_x->ctrl1_bit.ovfen = new_state;
  737. }
  738. /**
  739. * @brief init tmr input channel
  740. * @param tmr_x: select the tmr peripheral.
  741. * this parameter can be one of the following values:
  742. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR10,
  743. * TMR11, TMR12, TMR13, TMR14
  744. * @param input_struct
  745. * - to the structure of tmr_input_config_type
  746. * @param divider_factor
  747. * this parameter can be one of the following values:
  748. * - TMR_CHANNEL_INPUT_DIV_1
  749. * - TMR_CHANNEL_INPUT_DIV_2
  750. * - TMR_CHANNEL_INPUT_DIV_4
  751. * - TMR_CHANNEL_INPUT_DIV_8
  752. * @retval none
  753. */
  754. void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
  755. tmr_channel_input_divider_type divider_factor)
  756. {
  757. uint16_t channel = 0;
  758. /* get channel selected */
  759. channel = input_struct->input_channel_select;
  760. switch(channel)
  761. {
  762. case TMR_SELECT_CHANNEL_1:
  763. tmr_x->cctrl_bit.c1en = FALSE;
  764. tmr_x->cctrl_bit.c1p = (uint32_t)input_struct->input_polarity_select;
  765. tmr_x->cctrl_bit.c1cp = (input_struct->input_polarity_select & 0x2) >> 1;
  766. tmr_x->cm1_input_bit.c1c = input_struct->input_mapped_select;
  767. tmr_x->cm1_input_bit.c1df = input_struct->input_filter_value;
  768. tmr_x->cm1_input_bit.c1idiv = divider_factor;
  769. tmr_x->cctrl_bit.c1en = TRUE;
  770. break;
  771. case TMR_SELECT_CHANNEL_2:
  772. tmr_x->cctrl_bit.c2en = FALSE;
  773. tmr_x->cctrl_bit.c2p = (uint32_t)input_struct->input_polarity_select;
  774. tmr_x->cctrl_bit.c2cp = (input_struct->input_polarity_select & 0x2) >> 1;
  775. tmr_x->cm1_input_bit.c2c = input_struct->input_mapped_select;
  776. tmr_x->cm1_input_bit.c2df = input_struct->input_filter_value;
  777. tmr_x->cm1_input_bit.c2idiv = divider_factor;
  778. tmr_x->cctrl_bit.c2en = TRUE;
  779. break;
  780. case TMR_SELECT_CHANNEL_3:
  781. tmr_x->cctrl_bit.c3en = FALSE;
  782. tmr_x->cctrl_bit.c3p = (uint32_t)input_struct->input_polarity_select;
  783. tmr_x->cctrl_bit.c3cp = (input_struct->input_polarity_select & 0x2) >> 1;
  784. tmr_x->cm2_input_bit.c3c = input_struct->input_mapped_select;
  785. tmr_x->cm2_input_bit.c3df = input_struct->input_filter_value;
  786. tmr_x->cm2_input_bit.c3idiv = divider_factor;
  787. tmr_x->cctrl_bit.c3en = TRUE;
  788. break;
  789. case TMR_SELECT_CHANNEL_4:
  790. tmr_x->cctrl_bit.c4en = FALSE;
  791. tmr_x->cctrl_bit.c4p = (uint32_t)input_struct->input_polarity_select;
  792. tmr_x->cm2_input_bit.c4c = input_struct->input_mapped_select;
  793. tmr_x->cm2_input_bit.c4df = input_struct->input_filter_value;
  794. tmr_x->cm2_input_bit.c4idiv = divider_factor;
  795. tmr_x->cctrl_bit.c4en = TRUE;
  796. break;
  797. default:
  798. break;
  799. }
  800. }
  801. /**
  802. * @brief tmr channel enable
  803. * @param tmr_x: select the tmr peripheral.
  804. * this parameter can be one of the following values:
  805. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR10,
  806. * TMR11, TMR12, TMR13, TMR14
  807. * @param tmr_channel
  808. * this parameter can be one of the following values:
  809. * - TMR_SELECT_CHANNEL_1
  810. * - TMR_SELECT_CHANNEL_1C
  811. * - TMR_SELECT_CHANNEL_2
  812. * - TMR_SELECT_CHANNEL_2C
  813. * - TMR_SELECT_CHANNEL_3
  814. * - TMR_SELECT_CHANNEL_3C
  815. * - TMR_SELECT_CHANNEL_4
  816. * @param new_state (TRUE or FALSE)
  817. * @retval none
  818. */
  819. void tmr_channel_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, confirm_state new_state)
  820. {
  821. uint16_t channel;
  822. channel = tmr_channel;
  823. switch(channel)
  824. {
  825. case TMR_SELECT_CHANNEL_1:
  826. tmr_x->cctrl_bit.c1en = new_state;
  827. break;
  828. case TMR_SELECT_CHANNEL_1C:
  829. tmr_x->cctrl_bit.c1cen = new_state;
  830. break;
  831. case TMR_SELECT_CHANNEL_2:
  832. tmr_x->cctrl_bit.c2en = new_state;
  833. break;
  834. case TMR_SELECT_CHANNEL_2C:
  835. tmr_x->cctrl_bit.c2cen = new_state;
  836. break;
  837. case TMR_SELECT_CHANNEL_3:
  838. tmr_x->cctrl_bit.c3en = new_state;
  839. break;
  840. case TMR_SELECT_CHANNEL_3C:
  841. tmr_x->cctrl_bit.c3cen = new_state;
  842. break;
  843. case TMR_SELECT_CHANNEL_4:
  844. tmr_x->cctrl_bit.c4en = new_state;
  845. break;
  846. default:
  847. break;
  848. }
  849. }
  850. /**
  851. * @brief set tmr input channel filter
  852. * @param tmr_x: select the tmr peripheral.
  853. * this parameter can be one of the following values:
  854. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR10,
  855. * TMR11, TMR12, TMR13, TMR14
  856. * @param tmr_channel
  857. * this parameter can be one of the following values:
  858. * - TMR_SELECT_CHANNEL_1
  859. * - TMR_SELECT_CHANNEL_2
  860. * - TMR_SELECT_CHANNEL_3
  861. * - TMR_SELECT_CHANNEL_4
  862. * @param filter_value (0x0~0xf)
  863. * @retval none
  864. */
  865. void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
  866. uint16_t filter_value)
  867. {
  868. uint16_t channel;
  869. channel = tmr_channel;
  870. switch(channel)
  871. {
  872. case TMR_SELECT_CHANNEL_1:
  873. tmr_x->cm1_input_bit.c1df = filter_value;
  874. break;
  875. case TMR_SELECT_CHANNEL_2:
  876. tmr_x->cm1_input_bit.c2df = filter_value;
  877. break;
  878. case TMR_SELECT_CHANNEL_3:
  879. tmr_x->cm2_input_bit.c3df = filter_value;
  880. break;
  881. case TMR_SELECT_CHANNEL_4:
  882. tmr_x->cm2_input_bit.c4df = filter_value;
  883. break;
  884. default:
  885. break;
  886. }
  887. }
  888. /**
  889. * @brief config tmr pwm input
  890. * @param tmr_x: select the tmr peripheral.
  891. * this parameter can be one of the following values:
  892. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR10,
  893. * TMR11, TMR12, TMR13, TMR14
  894. * @param input_struct
  895. * - to the structure of tmr_input_config_type
  896. * @param divider_factor
  897. * this parameter can be one of the following values:
  898. * - TMR_CHANNEL_INPUT_DIV_1
  899. * - TMR_CHANNEL_INPUT_DIV_2
  900. * - TMR_CHANNEL_INPUT_DIV_4
  901. * - TMR_CHANNEL_INPUT_DIV_8
  902. * @retval none
  903. */
  904. void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
  905. tmr_channel_input_divider_type divider_factor)
  906. {
  907. uint16_t channel = 0;
  908. /* get channel selected */
  909. channel = input_struct->input_channel_select;
  910. switch(channel)
  911. {
  912. case TMR_SELECT_CHANNEL_1:
  913. if(input_struct->input_polarity_select == TMR_INPUT_RISING_EDGE)
  914. {
  915. /* set channel polarity */
  916. tmr_x->cctrl_bit.c1p = TMR_INPUT_RISING_EDGE;
  917. tmr_x->cctrl_bit.c2p = TMR_INPUT_FALLING_EDGE;
  918. }
  919. else if(input_struct->input_polarity_select == TMR_INPUT_FALLING_EDGE)
  920. {
  921. /* set channel polarity */
  922. tmr_x->cctrl_bit.c1p = TMR_INPUT_FALLING_EDGE;
  923. tmr_x->cctrl_bit.c2p = TMR_INPUT_RISING_EDGE;
  924. }
  925. if(input_struct->input_mapped_select == TMR_CC_CHANNEL_MAPPED_DIRECT)
  926. {
  927. /* ic1 is mapped on ti1 */
  928. tmr_x->cm1_input_bit.c1c = TMR_CC_CHANNEL_MAPPED_DIRECT;
  929. /* ic1 is mapped on ti2 */
  930. tmr_x->cm1_input_bit.c2c = TMR_CC_CHANNEL_MAPPED_INDIRECT;
  931. }
  932. else if(input_struct->input_mapped_select == TMR_CC_CHANNEL_MAPPED_INDIRECT)
  933. {
  934. /* ic1 is mapped on ti1 */
  935. tmr_x->cm1_input_bit.c1c = TMR_CC_CHANNEL_MAPPED_INDIRECT;
  936. /* ic1 is mapped on ti2 */
  937. tmr_x->cm1_input_bit.c2c = TMR_CC_CHANNEL_MAPPED_DIRECT;
  938. }
  939. /* set input ch1 and ch2 filter value*/
  940. tmr_x->cm1_input_bit.c1df = input_struct->input_filter_value;
  941. tmr_x->cm1_input_bit.c2df = input_struct->input_filter_value;
  942. /*set input ch1 and ch2 divider value*/
  943. tmr_x->cm1_input_bit.c1idiv = divider_factor;
  944. tmr_x->cm1_input_bit.c2idiv = divider_factor;
  945. tmr_x->cctrl_bit.c1en = TRUE;
  946. tmr_x->cctrl_bit.c2en = TRUE;
  947. break;
  948. case TMR_SELECT_CHANNEL_2:
  949. if(input_struct->input_polarity_select == TMR_INPUT_RISING_EDGE)
  950. {
  951. /* set channel polarity */
  952. tmr_x->cctrl_bit.c2p = TMR_INPUT_RISING_EDGE;
  953. tmr_x->cctrl_bit.c1p = TMR_INPUT_FALLING_EDGE;
  954. }
  955. else if(input_struct->input_polarity_select == TMR_INPUT_FALLING_EDGE)
  956. {
  957. /* set channel polarity */
  958. tmr_x->cctrl_bit.c2p = TMR_INPUT_FALLING_EDGE;
  959. tmr_x->cctrl_bit.c1p = TMR_INPUT_RISING_EDGE;
  960. }
  961. if(input_struct->input_mapped_select == TMR_CC_CHANNEL_MAPPED_DIRECT)
  962. {
  963. /* set mapped direct */
  964. tmr_x->cm1_input_bit.c2c = TMR_CC_CHANNEL_MAPPED_DIRECT;
  965. tmr_x->cm1_input_bit.c1c = TMR_CC_CHANNEL_MAPPED_INDIRECT;
  966. }
  967. else if(input_struct->input_mapped_select == TMR_CC_CHANNEL_MAPPED_INDIRECT)
  968. {
  969. /* set mapped direct */
  970. tmr_x->cm1_input_bit.c2c = TMR_CC_CHANNEL_MAPPED_INDIRECT;
  971. tmr_x->cm1_input_bit.c1c = TMR_CC_CHANNEL_MAPPED_DIRECT;
  972. }
  973. /* set input ch1 and ch2 filter value*/
  974. tmr_x->cm1_input_bit.c1df = input_struct->input_filter_value;
  975. tmr_x->cm1_input_bit.c2df = input_struct->input_filter_value;
  976. /*set input ch1 and ch2 divider value*/
  977. tmr_x->cm1_input_bit.c1idiv = divider_factor;
  978. tmr_x->cm1_input_bit.c2idiv = divider_factor;
  979. tmr_x->cctrl_bit.c1en = TRUE;
  980. tmr_x->cctrl_bit.c2en = TRUE;
  981. break;
  982. default:
  983. break;
  984. }
  985. }
  986. /**
  987. * @brief select tmr channel1 input
  988. * @param tmr_x: select the tmr peripheral.
  989. * this parameter can be one of the following values:
  990. * TMR1, TMR2, TMR3, TMR4
  991. * @param ch1_connect
  992. * this parameter can be one of the following values:
  993. * - TMR_CHANEL1_CONNECTED_C1IRAW
  994. * - TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR
  995. * @retval none
  996. */
  997. void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect)
  998. {
  999. tmr_x->ctrl2_bit.c1insel = ch1_connect;
  1000. }
  1001. /**
  1002. * @brief set tmr input channel divider
  1003. * @param tmr_x: select the tmr peripheral.
  1004. * this parameter can be one of the following values:
  1005. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR10,
  1006. * TMR11, TMR12, TMR13, TMR14
  1007. * @param tmr_channel
  1008. * this parameter can be one of the following values:
  1009. * - TMR_SELECT_CHANNEL_1
  1010. * - TMR_SELECT_CHANNEL_2
  1011. * - TMR_SELECT_CHANNEL_3
  1012. * - TMR_SELECT_CHANNEL_4
  1013. * @param divider_factor
  1014. * this parameter can be one of the following values:
  1015. * - TMR_CHANNEL_INPUT_DIV_1
  1016. * - TMR_CHANNEL_INPUT_DIV_2
  1017. * - TMR_CHANNEL_INPUT_DIV_4
  1018. * - TMR_CHANNEL_INPUT_DIV_8
  1019. * @retval none
  1020. */
  1021. void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
  1022. tmr_channel_input_divider_type divider_factor)
  1023. {
  1024. uint16_t channel;
  1025. channel = tmr_channel;
  1026. switch(channel)
  1027. {
  1028. case TMR_SELECT_CHANNEL_1:
  1029. tmr_x->cm1_input_bit.c1idiv = divider_factor;
  1030. break;
  1031. case TMR_SELECT_CHANNEL_2:
  1032. tmr_x->cm1_input_bit.c2idiv = divider_factor;
  1033. break;
  1034. case TMR_SELECT_CHANNEL_3:
  1035. tmr_x->cm2_input_bit.c3idiv = divider_factor;
  1036. break;
  1037. case TMR_SELECT_CHANNEL_4:
  1038. tmr_x->cm2_input_bit.c4idiv = divider_factor;
  1039. break;
  1040. default:
  1041. break;
  1042. }
  1043. }
  1044. /**
  1045. * @brief select tmr primary mode
  1046. * @param tmr_x: select the tmr peripheral.
  1047. * this parameter can be one of the following values:
  1048. * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7, TMR9, TMR12
  1049. * @param primary_mode
  1050. * this parameter can be one of the following values:
  1051. * - TMR_PRIMARY_SEL_RESET
  1052. * - TMR_PRIMARY_SEL_ENABLE
  1053. * - TMR_PRIMARY_SEL_OVERFLOW
  1054. * - TMR_PRIMARY_SEL_COMPARE
  1055. * - TMR_PRIMARY_SEL_C1ORAW
  1056. * - TMR_PRIMARY_SEL_C2ORAW
  1057. * - TMR_PRIMARY_SEL_C3ORAW
  1058. * - TMR_PRIMARY_SEL_C4ORAW
  1059. * @retval none
  1060. */
  1061. void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode)
  1062. {
  1063. tmr_x->ctrl2_bit.ptos = primary_mode;
  1064. }
  1065. /**
  1066. * @brief select tmr subordinate mode
  1067. * @param tmr_x: select the tmr peripheral.
  1068. * this parameter can be one of the following values:
  1069. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR12
  1070. * @param sub_mode
  1071. * this parameter can be one of the following values:
  1072. * - TMR_SUB_MODE_DIABLE
  1073. * - TMR_SUB_ENCODER_MODE_A
  1074. * - TMR_SUB_ENCODER_MODE_B
  1075. * - TMR_SUB_ENCODER_MODE_C
  1076. * - TMR_SUB_RESET_MODE
  1077. * - TMR_SUB_HANG_MODE
  1078. * - TMR_SUB_TRIGGER_MODE
  1079. * - TMR_SUB_EXTERNAL_CLOCK_MODE_A
  1080. * @retval none
  1081. */
  1082. void tmr_sub_mode_select(tmr_type *tmr_x, tmr_sub_mode_select_type sub_mode)
  1083. {
  1084. tmr_x->stctrl_bit.smsel = sub_mode;
  1085. }
  1086. /**
  1087. * @brief select tmr channel dma
  1088. * @param tmr_x: select the tmr peripheral.
  1089. * this parameter can be one of the following values:
  1090. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR10,
  1091. * TMR11, TMR12, TMR13, TMR14
  1092. * @param cc_dma_select
  1093. * this parameter can be one of the following values:
  1094. * - TMR_DMA_REQUEST_BY_CHANNEL
  1095. * - TMR_DMA_REQUEST_BY_OVERFLOW
  1096. * @retval none
  1097. */
  1098. void tmr_channel_dma_select(tmr_type *tmr_x, tmr_dma_request_source_type cc_dma_select)
  1099. {
  1100. tmr_x->ctrl2_bit.drs = cc_dma_select;
  1101. }
  1102. /**
  1103. * @brief select tmr hall
  1104. * @param tmr_x: select the tmr peripheral.
  1105. * this parameter can be one of the following values:
  1106. * TMR1, TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  1107. * @param new_state (TRUE or FALSE)
  1108. * @retval none
  1109. */
  1110. void tmr_hall_select(tmr_type *tmr_x, confirm_state new_state)
  1111. {
  1112. tmr_x->ctrl2_bit.ccfs = new_state;
  1113. }
  1114. /**
  1115. * @brief select tmr channel buffer
  1116. * @param tmr_x: select the tmr peripheral.
  1117. * this parameter can be one of the following values:
  1118. * TMR1, TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  1119. * @param new_state (TRUE or FALSE)
  1120. * @retval none
  1121. */
  1122. void tmr_channel_buffer_enable(tmr_type *tmr_x, confirm_state new_state)
  1123. {
  1124. tmr_x->ctrl2_bit.cbctrl = new_state;
  1125. }
  1126. /**
  1127. * @brief select tmr trgout2
  1128. * @param tmr_x: select the tmr peripheral.
  1129. * this parameter can be one of the following values:
  1130. * TMR1
  1131. * @param new_state (TRUE or FALSE)
  1132. * @retval none
  1133. */
  1134. void tmr_trgout2_enable(tmr_type *tmr_x, confirm_state new_state)
  1135. {
  1136. tmr_x->ctrl2_bit.trgout2en = new_state;
  1137. }
  1138. /**
  1139. * @brief select tmr sub-trigger
  1140. * @param tmr_x: select the tmr peripheral.
  1141. * this parameter can be one of the following values:
  1142. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR12
  1143. * @param trigger_select
  1144. * this parameter can be one of the following values:
  1145. * - TMR_SUB_INPUT_SEL_IS0
  1146. * - TMR_SUB_INPUT_SEL_IS1
  1147. * - TMR_SUB_INPUT_SEL_IS2
  1148. * - TMR_SUB_INPUT_SEL_IS3
  1149. * - TMR_SUB_INPUT_SEL_C1INC
  1150. * - TMR_SUB_INPUT_SEL_C1DF1
  1151. * - TMR_SUB_INPUT_SEL_C2DF2
  1152. * - TMR_SUB_INPUT_SEL_EXTIN
  1153. * @retval none
  1154. */
  1155. void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_select)
  1156. {
  1157. tmr_x->stctrl_bit.stis = trigger_select;
  1158. }
  1159. /**
  1160. * @brief set tmr subordinate synchronization mode
  1161. * @param tmr_x: select the tmr peripheral.
  1162. * this parameter can be one of the following values:
  1163. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR12
  1164. * @param new_state (TRUE or FALSE)
  1165. * @retval none
  1166. */
  1167. void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state)
  1168. {
  1169. tmr_x->stctrl_bit.sts = new_state;
  1170. }
  1171. /**
  1172. * @brief enable or disable tmr dma request
  1173. * @param tmr_x: select the tmr peripheral.
  1174. * this parameter can be one of the following values:
  1175. * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7,
  1176. * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  1177. * @param dma_request
  1178. * this parameter can be one of the following values:
  1179. * - TMR_OVERFLOW_DMA_REQUEST
  1180. * - TMR_C1_DMA_REQUEST
  1181. * - TMR_C2_DMA_REQUEST
  1182. * - TMR_C3_DMA_REQUEST
  1183. * - TMR_C4_DMA_REQUEST
  1184. * - TMR_HALL_DMA_REQUEST
  1185. * - TMR_TRIGGER_DMA_REQUEST
  1186. * @param new_state (TRUE or FALSE)
  1187. * @retval none
  1188. */
  1189. void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state)
  1190. {
  1191. if(new_state == TRUE)
  1192. {
  1193. tmr_x->iden |= dma_request;
  1194. }
  1195. else if(new_state == FALSE)
  1196. {
  1197. tmr_x->iden &= ~dma_request;
  1198. }
  1199. }
  1200. /**
  1201. * @brief enable or disable tmr interrupt
  1202. * @param tmr_x: select the tmr peripheral.
  1203. * this parameter can be one of the following values:
  1204. * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7,
  1205. * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  1206. * @param tmr_interrupt
  1207. * this parameter can be one of the following values:
  1208. * - TMR_OVF_INT
  1209. * - TMR_C1_INT
  1210. * - TMR_C2_INT
  1211. * - TMR_C3_INT
  1212. * - TMR_C4_INT
  1213. * - TMR_HALL_INT
  1214. * - TMR_TRIGGER_INT
  1215. * - TMR_BRK_INT
  1216. * @param new_state (TRUE or FALSE)
  1217. * @retval none
  1218. */
  1219. void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state)
  1220. {
  1221. if(new_state == TRUE)
  1222. {
  1223. tmr_x->iden |= tmr_interrupt;
  1224. }
  1225. else if(new_state == FALSE)
  1226. {
  1227. tmr_x->iden &= ~tmr_interrupt;
  1228. }
  1229. }
  1230. /**
  1231. * @brief get tmr flag
  1232. * @param tmr_x: select the tmr peripheral.
  1233. * this parameter can be one of the following values:
  1234. * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7,
  1235. * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  1236. * @param tmr_flag
  1237. * this parameter can be one of the following values:
  1238. * - TMR_OVF_FLAG
  1239. * - TMR_C1_FLAG
  1240. * - TMR_C2_FLAG
  1241. * - TMR_C3_FLAG
  1242. * - TMR_C4_FLAG
  1243. * - TMR_C5_FLAG
  1244. * - TMR_HALL_FLAG
  1245. * - TMR_TRIGGER_FLAG
  1246. * - TMR_BRK_FLAG
  1247. * - TMR_C1_RECAPTURE_FLAG
  1248. * - TMR_C2_RECAPTURE_FLAG
  1249. * - TMR_C3_RECAPTURE_FLAG
  1250. * - TMR_C4_RECAPTURE_FLAG
  1251. * @retval state of tmr flag
  1252. */
  1253. flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag)
  1254. {
  1255. flag_status status = RESET;
  1256. if((tmr_x->ists & tmr_flag) != RESET)
  1257. {
  1258. status = SET;
  1259. }
  1260. else
  1261. {
  1262. status = RESET;
  1263. }
  1264. return status;
  1265. }
  1266. /**
  1267. * @brief clear tmr flag
  1268. * @param tmr_x: select the tmr peripheral.
  1269. * this parameter can be one of the following values:
  1270. * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7,
  1271. * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  1272. * @param tmr_flag
  1273. * this parameter can be any combination of the following values:
  1274. * - TMR_OVF_FLAG
  1275. * - TMR_C1_FLAG
  1276. * - TMR_C2_FLAG
  1277. * - TMR_C3_FLAG
  1278. * - TMR_C4_FLAG
  1279. * - TMR_C5_FLAG
  1280. * - TMR_HALL_FLAG
  1281. * - TMR_TRIGGER_FLAG
  1282. * - TMR_BRK_FLAG
  1283. * - TMR_C1_RECAPTURE_FLAG
  1284. * - TMR_C2_RECAPTURE_FLAG
  1285. * - TMR_C3_RECAPTURE_FLAG
  1286. * - TMR_C4_RECAPTURE_FLAG
  1287. * @retval none
  1288. */
  1289. void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag)
  1290. {
  1291. tmr_x->ists = ~tmr_flag;
  1292. }
  1293. /**
  1294. * @brief generate tmr event
  1295. * @param tmr_x: select the tmr peripheral.
  1296. * this parameter can be one of the following values:
  1297. * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7,
  1298. * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  1299. * @param tmr_event
  1300. * this parameter can be one of the following values:
  1301. * - TMR_OVERFLOW_SWTRIG
  1302. * - TMR_C1_SWTRIG
  1303. * - TMR_C2_SWTRIG
  1304. * - TMR_C3_SWTRIG
  1305. * - TMR_C4_SWTRIG
  1306. * - TMR_HALL_SWTRIG
  1307. * - TMR_TRIGGER_SWTRIG
  1308. * - TMR_BRK_SWTRIG
  1309. * @retval none
  1310. */
  1311. void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event)
  1312. {
  1313. tmr_x->swevt |= tmr_event;
  1314. }
  1315. /**
  1316. * @brief tmr output enable(oen),this function is important for advtm output enable
  1317. * @param tmr_x: select the tmr peripheral.
  1318. * this parameter can be one of the following values:
  1319. * TMR1, TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  1320. * @param new_state (TRUE or FALSE)
  1321. * @retval none
  1322. */
  1323. void tmr_output_enable(tmr_type *tmr_x, confirm_state new_state)
  1324. {
  1325. tmr_x->brk_bit.oen = new_state;
  1326. }
  1327. /**
  1328. * @brief set tmr select internal clock
  1329. * @param tmr_x: select the tmr peripheral.
  1330. * this parameter can be one of the following values:
  1331. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR12
  1332. * @retval none
  1333. */
  1334. void tmr_internal_clock_set(tmr_type *tmr_x)
  1335. {
  1336. tmr_x->stctrl_bit.smsel = TMR_SUB_MODE_DIABLE;
  1337. }
  1338. /**
  1339. * @brief set tmr output channel polarity
  1340. * @param tmr_x: select the tmr peripheral.
  1341. * this parameter can be one of the following values:
  1342. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR10,
  1343. * TMR11, TMR12, TMR13, TMR14
  1344. * @param tmr_channel
  1345. * this parameter can be one of the following values:
  1346. * - TMR_SELECT_CHANNEL_1
  1347. * - TMR_SELECT_CHANNEL_2
  1348. * - TMR_SELECT_CHANNEL_3
  1349. * - TMR_SELECT_CHANNEL_4
  1350. * - TMR_SELECT_CHANNEL_1C
  1351. * - TMR_SELECT_CHANNEL_2C
  1352. * - TMR_SELECT_CHANNEL_3C
  1353. * @param oc_polarity
  1354. * this parameter can be one of the following values:
  1355. * - TMR_POLARITY_ACTIVE_HIGH
  1356. * - TMR_POLARITY_ACTIVE_LOW
  1357. * @retval none
  1358. */
  1359. void tmr_output_channel_polarity_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
  1360. tmr_polarity_active_type oc_polarity)
  1361. {
  1362. uint16_t channel;
  1363. channel = tmr_channel;
  1364. switch(channel)
  1365. {
  1366. case TMR_SELECT_CHANNEL_1:
  1367. tmr_x->cctrl_bit.c1p = (uint32_t)oc_polarity;
  1368. break;
  1369. case TMR_SELECT_CHANNEL_2:
  1370. tmr_x->cctrl_bit.c2p = (uint32_t)oc_polarity;
  1371. break;
  1372. case TMR_SELECT_CHANNEL_3:
  1373. tmr_x->cctrl_bit.c3p = (uint32_t)oc_polarity;
  1374. break;
  1375. case TMR_SELECT_CHANNEL_4:
  1376. tmr_x->cctrl_bit.c4p = (uint32_t)oc_polarity;
  1377. break;
  1378. case TMR_SELECT_CHANNEL_1C:
  1379. tmr_x->cctrl_bit.c1cp = (uint32_t)oc_polarity;
  1380. break;
  1381. case TMR_SELECT_CHANNEL_2C:
  1382. tmr_x->cctrl_bit.c2cp = (uint32_t)oc_polarity;
  1383. break;
  1384. case TMR_SELECT_CHANNEL_3C:
  1385. tmr_x->cctrl_bit.c3cp = (uint32_t)oc_polarity;
  1386. break;
  1387. default:
  1388. break;
  1389. }
  1390. }
  1391. /**
  1392. * @brief config tmr external clock
  1393. * @param tmr_x: select the tmr peripheral.
  1394. * this parameter can be one of the following values:
  1395. * TMR1, TMR2, TMR3, TMR4
  1396. * @param es_divide
  1397. * this parameter can be one of the following values:
  1398. * - TMR_ES_FREQUENCY_DIV_1
  1399. * - TMR_ES_FREQUENCY_DIV_2
  1400. * - TMR_ES_FREQUENCY_DIV_4
  1401. * - TMR_ES_FREQUENCY_DIV_8
  1402. * @param es_polarity
  1403. * this parameter can be one of the following values:
  1404. * - TMR_ES_POLARITY_NON_INVERTED
  1405. * - TMR_ES_POLARITY_INVERTED
  1406. * @param es_filter (0x0~0xf)
  1407. * @retval none
  1408. */
  1409. void tmr_external_clock_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
  1410. tmr_external_signal_polarity_type es_polarity, uint16_t es_filter)
  1411. {
  1412. tmr_x->stctrl_bit.esdiv = es_divide;
  1413. tmr_x->stctrl_bit.esp = es_polarity;
  1414. tmr_x->stctrl_bit.esf = es_filter;
  1415. }
  1416. /**
  1417. * @brief config tmr external clock mode1
  1418. * @param tmr_x: select the tmr peripheral.
  1419. * this parameter can be one of the following values:
  1420. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR12
  1421. * @param es_divide
  1422. * this parameter can be one of the following values:
  1423. * - TMR_ES_FREQUENCY_DIV_1
  1424. * - TMR_ES_FREQUENCY_DIV_2
  1425. * - TMR_ES_FREQUENCY_DIV_4
  1426. * - TMR_ES_FREQUENCY_DIV_8
  1427. * @param es_polarity
  1428. * this parameter can be one of the following values:
  1429. * - TMR_ES_POLARITY_NON_INVERTED
  1430. * - TMR_ES_POLARITY_INVERTED
  1431. * @param es_filter (0x0~0xf)
  1432. * @retval none
  1433. */
  1434. void tmr_external_clock_mode1_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
  1435. tmr_external_signal_polarity_type es_polarity, uint16_t es_filter)
  1436. {
  1437. tmr_external_clock_config(tmr_x, es_divide, es_polarity, es_filter);
  1438. tmr_x->stctrl_bit.smsel = TMR_SUB_EXTERNAL_CLOCK_MODE_A;
  1439. tmr_x->stctrl_bit.stis = TMR_SUB_INPUT_SEL_EXTIN;
  1440. }
  1441. /**
  1442. * @brief config tmr external clock mode2
  1443. * @param tmr_x: select the tmr peripheral.
  1444. * this parameter can be one of the following values:
  1445. * TMR1, TMR2, TMR3, TMR4
  1446. * @param es_divide
  1447. * this parameter can be one of the following values:
  1448. * - TMR_ES_FREQUENCY_DIV_1
  1449. * - TMR_ES_FREQUENCY_DIV_2
  1450. * - TMR_ES_FREQUENCY_DIV_4
  1451. * - TMR_ES_FREQUENCY_DIV_8
  1452. * @param es_polarity
  1453. * this parameter can be one of the following values:
  1454. * - TMR_ES_POLARITY_NON_INVERTED
  1455. * - TMR_ES_POLARITY_INVERTED
  1456. * @param es_filter (0x0~0xf)
  1457. * @retval none
  1458. */
  1459. void tmr_external_clock_mode2_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
  1460. tmr_external_signal_polarity_type es_polarity, uint16_t es_filter)
  1461. {
  1462. tmr_external_clock_config(tmr_x, es_divide, es_polarity, es_filter);
  1463. tmr_x->stctrl_bit.ecmben = TRUE;
  1464. }
  1465. /**
  1466. * @brief config tmr encoder mode
  1467. * @param tmr_x: select the tmr peripheral.
  1468. * this parameter can be one of the following values:
  1469. * TMR1, TMR2, TMR3, TMR4
  1470. * @param encoder_mode
  1471. * this parameter can be one of the following values:
  1472. * - TMR_ENCODER_MODE_A
  1473. * - TMR_ENCODER_MODE_B
  1474. * - TMR_ENCODER_MODE_C
  1475. * @param ic1_polarity
  1476. * this parameter can be one of the following values:
  1477. * - TMR_INPUT_RISING_EDGE
  1478. * - TMR_INPUT_FALLING_EDGE
  1479. * - TMR_INPUT_BOTH_EDGE
  1480. * @param ic2_polarity
  1481. * this parameter can be one of the following values:
  1482. * - TMR_INPUT_RISING_EDGE
  1483. * - TMR_INPUT_FALLING_EDGE
  1484. * - TMR_INPUT_BOTH_EDGE
  1485. * @retval none
  1486. */
  1487. void tmr_encoder_mode_config(tmr_type *tmr_x, tmr_encoder_mode_type encoder_mode, tmr_input_polarity_type \
  1488. ic1_polarity, tmr_input_polarity_type ic2_polarity)
  1489. {
  1490. tmr_x->stctrl_bit.smsel = encoder_mode;
  1491. /* set ic1 polarity */
  1492. tmr_x->cctrl_bit.c1p = (ic1_polarity & 0x1);
  1493. tmr_x->cctrl_bit.c1cp = (ic1_polarity >> 1);
  1494. /* set ic1 as input channel */
  1495. tmr_x->cm1_input_bit.c1c = TMR_CC_CHANNEL_MAPPED_DIRECT;
  1496. /* set ic2 polarity */
  1497. tmr_x->cctrl_bit.c2p = (ic2_polarity & 0x1);
  1498. tmr_x->cctrl_bit.c2cp = (ic2_polarity >> 1);
  1499. /* set ic2 as input channel */
  1500. tmr_x->cm1_input_bit.c2c = TMR_CC_CHANNEL_MAPPED_DIRECT;
  1501. }
  1502. /**
  1503. * @brief set tmr force output
  1504. * @param tmr_x: select the tmr peripheral.
  1505. * this parameter can be one of the following values:
  1506. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR10,
  1507. * TMR11, TMR12, TMR13, TMR14
  1508. * @param tmr_channel
  1509. * this parameter can be one of the following values:
  1510. * - TMR_SELECT_CHANNEL_1
  1511. * - TMR_SELECT_CHANNEL_2
  1512. * - TMR_SELECT_CHANNEL_3
  1513. * - TMR_SELECT_CHANNEL_4
  1514. * - TMR_SELECT_CHANNEL_5
  1515. * @param force_output
  1516. * this parameter can be one of the following values:
  1517. * - TMR_FORCE_OUTPUT_HIGH
  1518. * - TMR_FORCE_OUTPUT_LOW
  1519. * @retval none
  1520. */
  1521. void tmr_force_output_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
  1522. tmr_force_output_type force_output)
  1523. {
  1524. uint16_t channel;
  1525. channel = tmr_channel;
  1526. switch(channel)
  1527. {
  1528. case TMR_SELECT_CHANNEL_1:
  1529. tmr_x->cm1_output_bit.c1octrl = force_output;
  1530. break;
  1531. case TMR_SELECT_CHANNEL_2:
  1532. tmr_x->cm1_output_bit.c2octrl = force_output;
  1533. break;
  1534. case TMR_SELECT_CHANNEL_3:
  1535. tmr_x->cm2_output_bit.c3octrl = force_output;
  1536. break;
  1537. case TMR_SELECT_CHANNEL_4:
  1538. tmr_x->cm2_output_bit.c4octrl = force_output;
  1539. break;
  1540. case TMR_SELECT_CHANNEL_5:
  1541. tmr_x->cm3_output_bit.c5octrl = force_output;
  1542. break;
  1543. default:
  1544. break;
  1545. }
  1546. }
  1547. /**
  1548. * @brief config tmr dma control
  1549. * @param tmr_x: select the tmr peripheral.
  1550. * this parameter can be one of the following values:
  1551. * TMR1, TMR2, TMR3, TMR4, TMR9, TMR10,
  1552. * TMR11, TMR12, TMR13, TMR14
  1553. * @param dma_length
  1554. * this parameter can be one of the following values:
  1555. * - TMR_DMA_TRANSFER_1BYTE
  1556. * - TMR_DMA_TRANSFER_2BYTES
  1557. * - TMR_DMA_TRANSFER_3BYTES
  1558. * ...
  1559. * - TMR_DMA_TRANSFER_17BYTES
  1560. * - TMR_DMA_TRANSFER_18BYTES
  1561. * @param dma_base_address
  1562. * this parameter can be one of the following values:
  1563. * - TMR_CTRL1_ADDRESS
  1564. * - TMR_CTRL2_ADDRESS
  1565. * - TMR_STCTRL_ADDRESS
  1566. * - TMR_IDEN_ADDRESS
  1567. * - TMR_ISTS_ADDRESS
  1568. * - TMR_SWEVT_ADDRESS
  1569. * - TMR_CM1_ADDRESS
  1570. * - TMR_CM2_ADDRESS
  1571. * - TMR_CCTRL_ADDRESS
  1572. * - TMR_CVAL_ADDRESS
  1573. * - TMR_DIV_ADDRESS
  1574. * - TMR_PR_ADDRESS
  1575. * - TMR_RPR_ADDRESS
  1576. * - TMR_C1DT_ADDRESS
  1577. * - TMR_C2DT_ADDRESS
  1578. * - TMR_C3DT_ADDRESS
  1579. * - TMR_C4DT_ADDRESS
  1580. * - TMR_BRK_ADDRESS
  1581. * - TMR_DMACTRL_ADDRESS
  1582. * @retval none
  1583. */
  1584. void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, \
  1585. tmr_dma_address_type dma_base_address)
  1586. {
  1587. tmr_x->dmactrl_bit.dtb = dma_length;
  1588. tmr_x->dmactrl_bit.addr = dma_base_address;
  1589. }
  1590. /**
  1591. * @brief config tmr break mode and dead-time
  1592. * @param tmr_x: select the tmr peripheral.
  1593. * this parameter can be one of the following values:
  1594. * TMR1, TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
  1595. * @param brkdt_struct
  1596. * - to the structure of tmr_brkdt_config_type
  1597. * @retval none
  1598. */
  1599. void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct)
  1600. {
  1601. tmr_x->brk_bit.brken = brkdt_struct->brk_enable;
  1602. tmr_x->brk_bit.dtc = brkdt_struct->deadtime;
  1603. tmr_x->brk_bit.fcsodis = brkdt_struct->fcsodis_state;
  1604. tmr_x->brk_bit.fcsoen = brkdt_struct->fcsoen_state;
  1605. tmr_x->brk_bit.brkv = brkdt_struct->brk_polarity;
  1606. tmr_x->brk_bit.aoen = brkdt_struct->auto_output_enable;
  1607. tmr_x->brk_bit.wpc = brkdt_struct->wp_level;
  1608. }
  1609. /**
  1610. * @brief set tmr14 input channel remap
  1611. * @param tmr_x: select the tmr peripheral.
  1612. * this parameter can be one of the following values:
  1613. * TMR14
  1614. * @param input_remap
  1615. * - TMR14_GPIO
  1616. * - TMR14_ERTCCLK
  1617. * - TMR14_HEXT_DIV32
  1618. * - TMR14_CLKOUT
  1619. * @retval none
  1620. */
  1621. void tmr_iremap_config(tmr_type *tmr_x, tmr_input_remap_type input_remap)
  1622. {
  1623. if(tmr_x == TMR14)
  1624. {
  1625. tmr_x->rmp_bit.tmr14_ch1_irmp = input_remap;
  1626. }
  1627. }
  1628. /**
  1629. * @}
  1630. */
  1631. #endif
  1632. /**
  1633. * @}
  1634. */
  1635. /**
  1636. * @}
  1637. */