VGKitBoard_8270S/radio/A7169reg.h

/********************************************************************
*   A7169REG.h
*   RF Chip-A7169 Hardware Definitions
*
*   This file provides the constants associated with the
*   AMICCOM A7169 device.
*
********************************************************************/
#ifndef _A7169REG_h_
#define _A7169REG_h_
#include <stdint.h>



/**
 * 以下寄存器通过这个来操作：
 * 1、A7169_WriteReg
 */
#define SYSTEMCLOCK_REG     0x00
#define PLL1_REG            0x01
#define PLL2_REG            0x02
#define PLL3_REG            0x03
#define PLL4_REG            0x04
#define PLL5_REG            0x05
#define PLL6_REG            0x06
#define CRYSTAL_REG         0x07
#define PAGEA_REG           0x08
#define PAGEB_REG           0x09
#define RX1_REG             0x0A
#define RX2_REG             0x0B
#define ADC_REG             0x0C
#define PIN_REG             0x0D
#define CALIBRATION_REG     0x0E
#define MODE_REG            0x0F

/**
 * 以下寄存器通过这两个api来操作：
 * 1、写操作：A7169_WritePageA
 * 2、读操作：A7169_ReadPageA
 */
#define TX1_PAGEA           0x00
#define WOR1_PAGEA          0x01
#define WOR2_PAGEA          0x02
#define RFI_PAGEA           0x03
#define PM_PAGEA            0x04
#define RTH_PAGEA           0x05
#define AGC1_PAGEA          0x06
#define AGC2_PAGEA          0x07
#define GIO_PAGEA           0x08
#define CKO_PAGEA           0x09
#define VCB_PAGEA           0x0A
#define CHG1_PAGEA          0x0B
#define CHG2_PAGEA          0x0C
#define FIFO_PAGEA          0x0D
#define CODE_PAGEA          0x0E
#define WCAL_PAGEA          0x0F

/**
 * 以下寄存器通过这两个api来操作：
 * 1、写操作：A7169_WritePageB
 * 2、读操作：A7169_ReadPageB
 */
#define TX2_PAGEB           0x00
#define IF1_PAGEB           0x01
#define IF2_PAGEB           0x02
#define ACK_PAGEB           0x03
#define ART_PAGEB           0x04
#define SYN_PAGEB           0x05
#define RCCAL_PAGEB         0x06
#define ACKFIFO_PAGEB       0x07
#define PNCFG1_PAGEB        0x08
#define PNCFG2_PAGEB        0x09
#define PNCFG3_PAGEB        0x0A
#define PNCFG4_PAGEB        0x0B
#define PNCFG5_PAGEB        0x0C
#define TCODE_PAGEB         0x0D
#define PN_DC_PAGEB         0x0E
#define PNCFG6_PAGEB        0x0F
#define PNCFG7_PAGEB        0x10
#define PNCFG8_PAGEB        0x11
#define PNCFG9_PAGEB        0x12
#define PNCFG10_PAGEB       0x13
#define Misc_CFG1_PAGEB     0x14
#define Misc_CFG2_PAGEB     0x15
#define Misc_CFG3_PAGEB     0x16
#define PLL7_PAGEB          0x17
#define PLL8_PAGEB          0x18
#define PSMODE1_PAGEB       0x19
#define PSMODE2_PAGEB       0x1A
#define PSMODE3_PAGEB       0x1B
#define TX3_PAGEB           0x1C
#define Misc_CFG4_PAGEB     0x1D
#define PNCFG11_PAGEB       0x1E
#define PNCFG12_PAGEB       0x1F
#define PNCFG13_PAGEB       0x20
#define PNCFG14_PAGEB       0x21
#define PNCFG15_PAGEB       0x22
#define PNCFG16_PAGEB       0x23
#define PNCFG17_PAGEB       0x24
#define PNCFG18_PAGEB       0x25
#define CSMA1_PAGEB         0x26
#define CSMA2_PAGEB         0x27
#define TXPA_PAGEB          0x28
#define DCMON1_PAGEB        0x29
#define DCMON2_PAGEB        0x2A	
#define DCMON3_PAGEB        0x2B
#define MBUS1_PAGEB         0x2C
#define MBUS2_PAGEB         0x2D
#define MBUS3_PAGEB         0x2E
#define MBUS4_PAGEB         0x2F
#define MBUS5_PAGEB         0x30
#define PN_DC2_PAGEB        0x31
#define VCB2_PAGEB          0x32
#define PS_MODE4_PAGEB      0x33
#define WOR3_PAGEB          0x34

/**
 * 以下寄存器通过这个来操作：
 * 1、StrobeCMD
 */
#define CMD_Reg_W           0x00  //000x,xxxx control register write
#define CMD_Reg_R           0x80  //100x,xxxx control register read
#define CMD_ID_W            0x20  //001x,xxxx ID write
#define CMD_ID_R            0xA0  //101x,xxxx ID Read
#define CMD_FIFO_W          0x40  //010x,xxxx TX FIFO Write
#define CMD_FIFO_R          0xC0  //110x,xxxx RX FIFO Read
#define CMD_RF_RST          0xFF  //x111,xxxx RF reset
#define CMD_TFR             0x60  //0110,xxxx TX FIFO address pointrt reset
#define CMD_RFR             0xE0  //1110,xxxx RX FIFO address pointer reset

#define CMD_SLEEP           0x10  //0001,0000 SLEEP mode
#define CMD_IDLE            0x12  //0001,0010 IDLE mode
#define CMD_STBY            0x14  //0001,0100 Standby mode
#define CMD_PLL             0x16  //0001,0110 PLL mode
#define CMD_RX              0x18  //0001,1000 RX mode
#define CMD_TX              0x1A  //0001,1010 TX mode
//#define CMD_DEEP_SLEEP    0x1C  //0001,1100 Deep Sleep mode(tri-state)
#define CMD_DEEP_SLEEP      0x1F  //0001,1111 Deep Sleep mode(pull-high)

//@RX2_REG
typedef union 
{
    uint16_t value;
    struct 
    {
        uint16_t DCM : 2;   //  [1:0]: Demodulator DC estimation mode. Recommend DCM = [01].
                            // [00]: By DC average value, DCV[7:0],(0Bh).
                            // [01]: DC holds after preamble detected.
                            // [10]: DC holds after ID detected.
                            // [11]: DC value when chip receive specific data length (set by DCL[:2:0])..
        uint16_t DCL : 3;// [2:0]: Data Length of Peak Detect average setting. Recommend DCL = [010].
                            // DCL[2:0] is used to let A7169 detects n times “0” or n times ”1” to result DC estimation voltage of demodulator.
                            // DCL[2:0]    |          DC average
                            //             |  Before ID Sync | After ID Sync
                            //     000     |       4         |     32
                            //     001     |       8         |     32
                            //     010     |       16        |     32
                            //     011     |       32        |     32
                            //     100     |       4         |     64
                            //     101     |       8         |     64
                            //     110     |       16        |     64
                            //     111     |       32        |     64
                            // For example, if DCL[2:0] = 000,
                            // Before ID sync, by peak detect method to update a new DC value for every 4 times 1” and 4 times ”0” .
                            // After ID sync, by peak detect method, to update a new DC value for every 32 times “1” and 32 times ”0” .
        uint16_t PMD : 3; // [2:0]: Preamble pattern detection. Recommend PMD = [100].
                            // When DCM[1:0] = 01, 10, 11, chip will execute preamble length detection automatically.
                            // [000]: 0 bit (Note: When PMD=[000], DC is not hold after ID detected.)
                            // [001]: 4 bits
                            // [010]: 8 bits (Default value)
                            // [011]: 16 bits
                            // [100]: 24 bits.
                            // [101] and [11x]: 32bits.
                        // Remark detection length setting should be smaller than the setting value of PML[1:0](08h, Page 14).
        uint16_t DCV : 8; // [7:0]: Data DC average value setting. Recommend DCV = [10010].
                            // This setting is only active when DCM (09h) = [00].
    }bits_w;
    struct 
    {
        uint16_t remark : 7; //
        uint16_t ADCO : 9;  // [8:0]: RSSI value if AGC =1 (Read Only).
    }bits_r;
}rx2_tu;
//@WOR1_PAGEA
typedef union 
{
    uint16_t value;
    struct 
    {
        uint16_t WOR_AC : 9;  //  [15:0]: 16-bits WOR Active Period.
                    // WOR_AC[15:9] is located in 0x09h, page 52.
                    // WOR_AC[8:6] is located in 0x09h, page 5.
                    // WOR Active Period = (WOR_AC[15:0]+1) x (1/4096), (244us ~ 16s).
        uint16_t WOR_SL : 9;  //  [15:0]: 16-bits WOR Sleep Period.
                    // WOR_SL[15:10] is located in 0x09h, page 52.
                    // WOR Sleep Period = (WOR_SL[15:0]+1) x (32/4096), (7.8ms ~ 512s)
    }bits_w;
}pageA_wor1_tu;
//@CODE_PAGEA
typedef union 
{
    uint16_t value;
    struct 
    {
        uint16_t PML : 3; // [2:0] (bit 15 / 1 / 0): Preamble Length Select. Recommend PML= [011].
                            // [000]: 1 byte.
                            // [001]: 2 bytes.
                            // [010]: 3 bytes.
                            // [011]: 4 bytes.
                            // [100]: 16 byte.
                            // [101]: 32 bytes.
                            // [110]: 48 bytes.
                            // [111]: 64 bytes.
        uint16_t IDL1 : 1; // [1:0] (bit 14 / 2): ID code length setting. Recommend IDL=[01].
                            // IDL [1:0] = [Bit14, Bit2].
                            // [00]: 2 bytes.
                            // [01]: 4 bytes.
                            // [10]: 6 bytes.
                            // [11]: 8 bytes.
        uint16_t WS : 7; // [6:0]: Data Whitening Seed (data encryption key, only for FIFO mode).
        uint16_t MCS : 1; //: Manchester Code Enable (Only for FIFO mode).
                            // [0]: Disable.
                            // [1]: Enable.
        uint16_t WHTS : 1; //: Data Whitening (Data Encryption, only for FIFO mode).
                            // [0]: Disable.
                            // [1]: Enable (The data is whitened by multiplying with PN7).
        uint16_t IDL0 : 1; // 
        uint16_t FECS : 1; // : FEC Select (Only for FIFO mode).
                            // [0]: Disable.
                            // [1]: Enable (The FEC is (7, 4) Hamming code).
        uint16_t CRCS : 1; // : CRC Select (Only for FIFO mode).
                            // [0]: Disable.
                            // [1]: Enable.
    }bits_w;
}pageA_code_tu;

typedef enum
{
    GIOMD_WTR,
    GIOMD_EOAC_FSYNC,
    GIOMD_TMEO_CD,
    GIOMD_PDN_PA,
    GIOMD_TWOR,
    GIOMD_SDO,
    GIOMD_TRXD,
    GIOMD_RXD,
    GIOMD_NC1,
    GIOMD_PDNRX,
    GIOMD_NC2,
    GIOMD_VPOAK,
    GIOMD_WATCH,
    GIOMD_PDNTX,
    GIOMD_FMTDO,
}gioModeSlt_e;
//@GIO_PAGEA
typedef union 
{
    uint16_t value;
    struct 
    {
        uint16_t g1oe : 1;    // : GIO1pin output enable.
                    // [0]: High Z.
                    // [1]: Enable.
        uint16_t g1i : 1;    // : GIO1 pin output signal invert.
                    // [0]: Non-inverted output.
                    // [1]: Inverted output.
        uint16_t gio1s : 4;    // [3:0]: GIO1 pin function select.
                                // GIO1S [3:0]         |   TX state    |   RX state
                                // [0000]              |   WTR (Wait until TX or RX finished)
                                // [0001]              |   EOAC (end of access code)       |   FSYNC (frame sync)
                                // [0010]              |   TMEO (TX modulation enable)     |   CD (carrier detect)
                                // [0011]              |   PDN_PA, when PASW=1
                                //                     |   Preamble Detect Output (PMDO), when PASW =0
                                // [0100]              |   TWOR, when TWOR mode enabled
                                //                     |   CWTR (Cyclic TRX edge WTR), when TWOR disabled
                                // [0101]              |   In phase demodulator input (DMII) or DVT[0](AGC)
                                // [0110]              |   SDO (4 wires SPI data out)
                                // [0111]              |   TRXD In/Out (Direct mode)
                                // [1000]              |   RXD (Direct mode)
                                // [1001]              |   0
                                // [1010]              |   PDN_RX
                                // [1011]              |   0
                                // [1100]              |   VPOAK (Valid Packet or Auto ACK OK Output)
                                // [1101]              |   WATCH
                                //                     |   WATCH_Sel[1:0] is located in 0x09h, page20.
                                //                     |   WATCH_Sel = [00] -> FPF
                                //                     |   WATCH_Sel = [01] -> WE_MAN
                                //                     |   WATCH_Sel = [10] -> WE_PN
                                //                     |   WATCH_Sel = [11] -> MAN_Sleep | PN_Sleep | FEC_Sleep
                                // [1110]              |   PDN_TX
                                // [1111]              |   FMTDO (FIFO mode TX Data Output testing)
        uint16_t g2oe : 1;    //: GIO2 pin output enable.
                            // [0]: High Z.
                            // [1]: Enable.
        uint16_t g2i : 1;    //: GIO2 pin output signal invert.
                            // [0]: Non-inverted output.
                            // [1]: Inverted output.
        uint16_t gio2s : 4;    //[3:0]: GIO2 pin function select.
                                // GIO2S [3:0]     |   TX state                        |   RX state
                                // [0000]          |   WTR (Wait until TX or RX finished)
                                // [0001]          |   EOAC (end of access code)       |   FSYNC (frame sync)
                                // [0010]          |   TMEO (TX modulation enable)     |   CD (carrier detect)
                                // [0011]          |   PDN_PA, when PASW=1 Preamble Detect Output (PMDO), when PASW =0
                                // [0100]          |   TWOR, when TWOR mode enabled
                                //                 |   CWTR (Cyclic TRX edge WTR), when TWOR disabled
                                // [0101]          |   Quadrature phase demodulator input (DMII) or DVT[0](AGC)
                                // [0110]          |   SDO (4 wires SPI data out)
                                // [0111]          |   TRXD In/Out (Direct mode)
                                // [1000]          |   RXD (Direct mode)
                                // [1001]          |   0
                                // [1010]          |   PDN_TX
                                // [1011]          |   0
                                // [1100]          |   VPOAK (Valid Packet or Auto ACK OK Output)
                                // [1101]          |   WATCH
                                //                 |   WATCH_Sel[1:0] is located in 0x09h, page20.
                                //                 |   WATCH_Sel = [00] -> FPF
                                //                 |   WATCH_Sel = [01] -> WE_MAN
                                //                 |   WATCH_Sel = [10] -> WE_PN
                                //                 |   WATCH_Sel = [11] -> MAN_Sleep | PN_Sleep | FEC_Sleep
                                // [1110]          |   Battery Detect flag. (BDF)
                                // [1111]          |   FMRDI. (FIFO mode RX input for testing) (for internal testing)
        uint16_t ddpc : 1;    //(Direct mode data pin control): Direct mode modem data can be accessed via SDIO pin.
                            // [0]: Disable.
                            // [1]: Enable.
        uint16_t mcnt : 1;   //[1:0]: Main Clock Divider.
                            // [00]: =
                            // [01]: = / 2
                            // [10]: = / 3
                            // [11]: = / 4
                            // Please refer to Chapter 12 for details.
        uint16_t wrcks : 1;   //: WOR Reference clock select.
                            // [0]: WOR Ref clock when PF8M is equal or close to 6.4MHz.
                            // [1]: WOR Ref clock when PF8M is equal or close to 8MHz.
    }bits_w;
}pageA_gio_tu;
//@PLL1_REG
typedef union 
{
    uint16_t value;
    struct 
    {
        uint16_t ip : 9;   //LO frequency Integer Part setting.
        uint16_t chi : 2;   //Reserved. CHI shall be [00].
        uint16_t chf : 2;   // Charge-pump current setting for fractional-N synthesizer. Recommend CHF = [01].
                            // [00]: 48uA
                            // [01]: 96uA
                            // [10]: 192uA
                            // [11]: 384uA
        uint16_t chi2i : 1;   //Reserved. CHI2I shall be [0].
        uint16_t chf2i : 1;   //Reserved. CHI2F shall be [0].
        uint16_t crcinv : 1;   // CRC Inverted Select.
                                // [0]: Disable.
                                // [1]: Enable 
    }bits_w;
}pll1_tu;
//@PLL4_REG
typedef union 
{
    uint16_t value;
    struct 
    {
        uint16_t EDI    : 1;   // Dither Noise setting. Recommend EDI = [0].
                                // [0]: Disable.
                                // [1]: Enable.
        uint16_t NSDO   : 1;   // Mash sigma delta order setting. Recommend NSDO = [0].
                            // [0]: Order 2.
                            // [1]: Order 3.
        uint16_t SDPW   : 2;   // Pulse Width of sigma-delta modulator. SDPW shall be [00].
        uint16_t ISDIV  : 1;   // Divider current test bit. Recommend ISDIV = [0].
                                // [0]: Low current.
                                // [1]: High current.
        uint16_t CPS    : 1;   // Charge Pump tri-state setting. Recommend CPS = [1].
                                // [0]: Tri-state.
                                // [1]: Normal operation.
        uint16_t VCI    : 1;   // VCO current calibration test bit. Reserved. VCl shall be [0].
        uint16_t ADCR   : 1;   // Reserved. ADCR should be= [0].
        uint16_t MD0    : 1;   // LO Buffer current select.
                                // [0]: Low current .
                                // [1]: High current.
        uint16_t PDL    : 3;   // PLL Settling Delay Time setting.
                                    // PDL [2:0] PLL Delay Timer   Note
                                    // 000         20 us
                                    // 001         40 us
                                    // 010         60 us
                                    // 011         80 us           Recommend
                                    // 100         100 us
                                    // 101         120 us
                                    // 110         140 us
                                    // 111         160 us
        uint16_t MD1    : 1;   // RF Band select.
                                // [0]: Low band (310MHz ~ 510MHz)
                                // [1]: High band (860MHz ~ 930MHz)
        uint16_t CKX2   : 1;   // Reserved. CKX2 shall be [0].
        uint16_t EDIVS  : 1;   // Synthesizer Selection. EDIVS shall be [0].
                                // [0]: Fractional-N PLL.
                                // [1]: Reserved.
        uint16_t TXDBG  : 1;   // TX Debug mode. TXDBG shall be [0].
                                // [0]: Disable.
                                // [1]: Enable.
    }bits_w;
}pll4_tu;
//@TX2_PAGEB
typedef union 
{
    uint16_t value;
    struct 
    {
        uint16_t tbg0_2 : 3;   //TX Buffer Gain setting.
                            // TBG [5:3] is located in 0x09h, page 21.
                            // Please refer to Chapter 8 and A7169 App. Note for programmable TX output power.
        uint16_t tdc : 2;   //TX Driver current setting.
                            // Please refer to Chapter 8 and A7169 App. Note for programmable TX output power.
        uint16_t pac : 2;   //PA current setting.
                            // Please refer to Chapter 8 and A7169 App. Note for programmable TX output power
        uint16_t txdi : 1;  //TX data inverted. Recommend TXDI = [0].
                            // [0]: Normal.
                            // [1]: Invert
        uint16_t tdl : 2;   //TX Settling Delay select.
        uint16_t bt : 2;    //Moving average for Gaussian filter select.
                            // If GS = [0],
                            // Gaussian filter is disabled,
                            // BT = [00]: not average.
                            // [01]: 2 bit average.
                            // [10]: 4 bit average.
                            // [11]: 8 bit average
                            // That means BT is used to smooth TX data transition.
                            // If GS = [1],
                            // Gaussian filter is enabled, and crystal frequency is 12.8MHz, DMOS=1
                            // BT = [00]: 2.0.
                            // [01]: 1.0.
                            // [10]: 0.5.
                            // [11]: 0.5
                            // If crystal frequency is 16MHz, DMOS=1
                            // BT = [00]: 1.0.
                            // [01]: 0.5.
                            // That means BT is used to configure shape of Gaussian filter.
        uint16_t dpr : 3;   //Scaling of PDL and TDL. Recommend DPR = [00000].
                                // DPR[4:3] is located in 0x09h, page 40.
        uint16_t mcntr : 1; //Divided by 2 select
    }bits_w;
    uint16_t did;   //Device ID data. (Read Only).
}pageB_tx2_tu;
//@Misc_CFG2_PAGEB
typedef union 
{
    uint16_t value;
    struct 
    {
        uint16_t dc_diff : 5;   //
        uint16_t dc_dth : 1;   //
        uint16_t man_sel : 1;   //
        uint16_t man_start : 1;   //
        uint16_t tbg3_5 : 3;   //
        uint16_t exdis : 1;   //
        uint16_t pn_start : 1;   //
        uint16_t raw_sel : 1;   //
        uint16_t rev : 2;   //
    }bits_w;
}pageB_misc_cfg2_tu;
//@MODE_REG
typedef union 
{
    uint16_t value;
    struct 
    {
        uint16_t adcm : 1;  //ADC measurement (Auto clear when done).
                            // [0]: Disable
                            // [1]: Enable.
        uint16_t fbc : 1;   //IF Filter Bank calibration enable (Auto clear when done).
                            // [0]: Disable .
                            // [1]: Enable.
        uint16_t vbc : 1;   //VCO Bank calibration enable (Auto clear when done).
                            // [0]: Disable.
                            // [1]: Enable.
        uint16_t trer : 1;  //TRX mode enable by register. Shall be set to [1].
                            // [0]: Reserved.
                            // [1]: By register control (CER and TRSR). In FIFO mode, this bit will be cleared after end of packet encountered.
        uint16_t trsr : 1;  //TRX Mode select by register.
                            // [0]: RX mode.
                            // [1]: TX mode.
                            // When bit TRER=1, the chip will enter TX or RX mode by TRSR register
        uint16_t plle : 1;  //PLL enable by register.
                            // [0]: PLL off.
                            // [1]: PLL on
        uint16_t cer : 1;   //Crystal enable by register.
                            // [0]: crystal turn-off.
                            // [1]: crystal turn-on.
        uint16_t fms : 1;   //Direct/FIFO mode select.
                            // [0]: Direct mode.
                            // [1]: FIFO mode.
        uint16_t fmt : 1;   //Reserved for internal usage only. Shall be set to [0]. 
        uint16_t wore : 1;  //WOT/WOR function enable.
                            // [0]: Disable.
                            // [1]: Enable
        uint16_t cce : 1;   //: Chip enable by register.
                            // [0]: chip turn-off.
                            // [1]: chip turn-on.
        uint16_t vcc : 1;   //VCO current calibration.
                            // [0]: Disable
                            // [1]: Enable
        uint16_t rssc : 1;  //RSSI Calibration.
                            // [0]: Disable.
                            // [1]: Enable.
        uint16_t swt : 1;   //VCO Current and ADC clock and System clock select. Recommend SWT = [0].
                            // [0]: Original
                            // [1]: Update
        uint16_t vbs : 1;   //Reserved. Should set to [0].
        uint16_t dfcd : 1;  //Packet Filtering by Carrier Detect.
                            // The received packet is filtered if the input power level is below RTH (0Ah).
                            // [0]: Disable.
                            // [1]: Enable. 
    }bits_w;
}base_modeControl_tu;
//@TX1_PAGEA
typedef union 
{
    uint16_t value;
    struct 
    {
        uint16_t fd : 8;  //TX Frequency Deviation setting.
                            // For both Gaussian filter is enabled (GS =1) or disabled（GS = 0）
        uint16_t fdp : 3;  // Frequency Deviation Exponential Coefficient setting.
        uint16_t gs  : 1;   //Gaussian Filter Selection.
                            // [0]: Disable.
                            // [1]: Enable.
        uint16_t tme  : 1;  //TX Modulation Enable.
                                // [0]: Disable.
                                // [1]: Enable.
        uint16_t rc_dly  : 3;  //RSSI calibration RL Delay setting. Recommend RC_DLY= [000].
                                // [000]: 100us.
                                // [001]: 300us.
                                // [010]: 500us.
                                // [011]: 700us.
                                // [100]: 900us.
                                // [101]: 1.1ms.
                                // [110]: 1.3ms.
                                // [111]: 1.5ms.
    }bits_w;
}pageA_tx1_tu;
//@FIFO_PAGEA
typedef union 
{
    uint16_t value;
    struct 
    {
        uint16_t FEP : 8;   //FIFO End Pointer for TX FIFO and Rx FIFO.
                            // Where FEP[7:0] are located at here and FEP[13:8] are located at 08h page 10.
                            // FIFO Length Setting = (FEP [13:0] +1).
                            // For example, if FEP = 0x3F, it means FIFO length is 64 bytes.
                            // For FIFO extension mode, FEP’s value shall be set larger than 0x3F.
                            // Please refer to section 16.4.2 for details
        uint16_t PSA : 6;   //Used for Segment FIFO.
                            // Used in FIFO segment mode
        uint16_t FPM : 2;   //FIFO Pointer Margin.
                            // FPM is used in FIFO extension mode for an indicator.
                            // FPM[1:0] Bytes in TX FIFO    Bytes in RX FIFO
                            //      [00]    4                   60
                            //      [01]    8                   56
                            //      [10]    12                  52
                            //      [11]    16                  48
    }bits_w;
}pageA_fifo_tu;
#endif