VGKitBoard_55xxS/radio/myRadio.h

#ifndef __MY_RADIO_H
#define __MY_RADIO_H
/* Includes ------------------------------------------------------------------*/
#include <stdio.h>
#include <stdbool.h>
#include <stdint.h>
#include <string.h>

#define MAX_RF_PACKET_LEN 128


typedef enum
{
    RF_TX_PWR_N_7,
    RF_TX_PWR_N_6,
    RF_TX_PWR_N_5,
    RF_TX_PWR_N_4,
    RF_TX_PWR_N_3,
    RF_TX_PWR_N_2,
    RF_TX_PWR_N_1,
    RF_TX_PWR_P_0,
    RF_TX_PWR_P_1,
    RF_TX_PWR_P_2,
    RF_TX_PWR_P_3,
    RF_TX_PWR_P_4,
    RF_TX_PWR_P_5,
    RF_TX_PWR_P_6,
    RF_TX_PWR_P_7,
    RF_TX_PWR_P_8,
    RF_TX_PWR_P_9,
    RF_TX_PWR_P_10,
    RF_TX_PWR_P_11,
    RF_TX_PWR_P_12,
    RF_TX_PWR_P_13,
    RF_TX_PWR_P_14,
    RF_TX_PWR_P_15,
    RF_TX_PWR_P_16,
    RF_TX_PWR_P_17,
    RF_TX_PWR_P_18,
    RF_TX_PWR_P_19,
    RF_TX_PWR_P_20,
    RF_TX_PWR_MAX_COUNT,
}rf_txPwr_te;
typedef enum
{
    DVTP_SI4438_C2A_433,
    DVTP_SI4438_C2A_490,
    DVTP_SI4463_C2A_433,
    DVTP_SI4463_C2A_490,
    DVTP_SI4463_C2A_868,
    DVTP_SI4463_C2A_915,
    DVTP_SI4438_B1C_433,
    DVTP_SI4438_B1C_490,
    DVTP_SI4463_B1B_433,
    DVTP_SI4463_B1B_868,
    DVTP_SI4463_B1B_915,
    DVTP_CUSTTOM,
    DVTP_MAX_COUNT,
}deviceType_te;

typedef enum
{
    RF_BAUDRATE_10000,    //
    MAX_RF_BAUDRATE_COUNT,    //
}rfBaudrate_te;
typedef enum
{
    FREQ_BAND_315,
    FREQ_BAND_433,
    FREQ_BAND_490,
    FREQ_BAND_868,
    FREQ_BAND_915,
    MAX_FREQ_BAND_COUNT,
}freqBand_te;

typedef union 
{
    uint8_t regValue;
    struct 
    {
        /** bit0
         * ...
         * bit7 */
        uint8_t GPIO_MODE : 6;   //Selects the level of drive strength for those GPIO/NIRQ/SDO pins configured as outputs.
                                // The selected level of drive strength is applied simultaneously to all output pins, with 
                                // the following exception: GPIO0 will exhibit a weaker drive strength than the other GPIO pins 
                                // but only in the lowest drive strength setting; its drive strength is the same for all other settings.
                                //@ SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO_GPIO_MODE_ENUM_DONOTHING
        uint8_t PULL_CTL : 1;   //The pin pull-up control.
                                //@ SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO_PULL_CTL_ENUM_PULL_DIS
        uint8_t RESERVER : 1;    //
    }unit;
}gpio_pin_cfg_tu;
typedef union 
{
    uint8_t regValue;
    struct 
    {
        /** bit0
         * ...
         * bit7 */
        uint8_t NIRQ_MODE : 6;   //Selects the level of drive strength for those GPIO/NIRQ/SDO pins configured as outputs.
                                // The selected level of drive strength is applied simultaneously to all output pins, with 
                                // the following exception: GPIO0 will exhibit a weaker drive strength than the other GPIO pins 
                                // but only in the lowest drive strength setting; its drive strength is the same for all other settings.
                                //@ SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_NIRQ_MODE_ENUM_DONOTHING
        uint8_t PULL_CTL : 1;   //The pin pull-up control.
                                //@ SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_PULL_CTL_ENUM_PULL_DIS
        uint8_t RESERVER : 1;    //
    }unit;
}nirq_pin_cfg_tu;
typedef union 
{
    uint8_t regValue;
    struct 
    {
        /** bit0
         * ...
         * bit7 */
        uint8_t SDO_MODE : 6;   //Selects the level of drive strength for those GPIO/NIRQ/SDO pins configured as outputs.
                                // The selected level of drive strength is applied simultaneously to all output pins, with 
                                // the following exception: GPIO0 will exhibit a weaker drive strength than the other GPIO pins 
                                // but only in the lowest drive strength setting; its drive strength is the same for all other settings.
                                //@ SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_SDO_MODE_ENUM_DONOTHING
        uint8_t PULL_CTL : 1;   //The pin pull-up control.
                                //@ SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_ENUM_PULL_DIS
        uint8_t RESERVER : 1;    //
    }unit;
}sdo_pin_cfg_tu;
typedef union 
{
    uint8_t regValue;
    struct 
    {
        /** bit0
         * ...
         * bit7 */
        uint8_t RESERVER1 : 5;   //
        uint8_t DRV_STRENGTH : 2;   //Reads back the enumeration of the currently selected drive strength.
                                    //@ SI446X_CMD_GPIO_PIN_CFG_ARG_GEN_CONFIG_DRV_STRENGTH_ENUM_HIGH
        uint8_t RESERVER2 : 1;    //
    }unit;
}gen_config_tu;
typedef union 
{
    uint8_t regValue;
    struct 
    {
        /** bit0
         * ...
         * bit7 */
        uint8_t DST_FIELD : 3;
        uint8_t IN_FIFO : 1;
        uint8_t SIZE : 1;
        uint8_t ENDIAN : 1;
        uint8_t INFINITE_LEN : 1;
        uint8_t RESERVER : 1;
    }unit;
}pkt_len_tu;
typedef union 
{
    uint8_t regValue;
    struct 
    {
        /** bit0
         * ...
         * bit7 */
        uint8_t SRC_FIELD : 1;
        uint8_t RESERVER : 7;
    }unit;
}pkt_len_field_source_tu;
typedef enum
{
    MODTPE_CW,
    MODTPE_OOK,
    MODTPE_2FSK,
    MODTPE_2GFSK,
    MODTPE_4FSK,
    MODTPE_4GFSK,
}mod_type_te;
typedef enum
{
    MODSRC_PACKET,  //The modulation is sourced from the TX FIFO in the packet handler.
    MODSRC_DIRECT,  //The modulation is sourced in real-time (i.e., TX Direct Mode) from a GPIO pin, as selected by the TX_DIRECT_MODE_GPIO field.
    MODSRC_PSEUDO,  //The modulation is sourced from the internal pseudo-random generator.
}mod_sourse_te;
typedef enum
{
    MODGPIO_GPIO0,  //TX direct mode uses GPIO0 as data source.
    MODGPIO_GPIO1,  //TX direct mode uses GPIO1 as data source.
    MODGPIO_GPIO2,  //TX direct mode uses GPIO2 as data source.
    MODGPIO_GPIO3,  //TX direct mode uses GPIO3 as data source.
}mod_gpio_te;
typedef enum
{
    DRCTMODTY_SYNC,    //Direct mode operates in synchronous mode, applies to TX only.   
    DRCTMODTY_ASYNC,   //Direct mode operates in asynchronous mode, applies to TX only. GFSK is not supported.
}direct_mode_type_te;
typedef union 
{
    uint8_t regValue;
    struct 
    {
        /** bit0
         * ...
         * bit7 */
        mod_type_te MOD_TYPE : 3;//This field configures the Modem for transmission or reception of the desired type of modulation.
                              // With the exception of CW mode (a TX-only function), this bit is applicable in both TX and RX modes.
        mod_sourse_te MOD_SOURCE : 2; //This bit selects the source of modulation during TX mode. It is applicable only in TX mode.
        mod_gpio_te TX_DIRECT_MODE_GPIO : 2; //This field determines which GPIO pin is selected by the Modem as the modulation data source during TX Direct mode. This bit is applicable only in TX mode, and only when the MOD_SOURCE field is also set for TX Direct mode.
                                // This field does not automatically configure the selected GPIO pin as a digital input pin; it remains necessary to additionally configure the desired GPIO pin as a CMOS-compatible input pin by setting GPIO_PIN_CFG=0x04.
        direct_mode_type_te TX_DIRECT_MODE_TYPE : 1; //This bit determines whether a real-time TX data stream (applied to the chip on a selected GPIO input pin) is processed in synchronous or asynchronous fashion. This bit is applicable only in TX mode, and only when the MOD_SOURCE field is also set for TX Direct mode.
                                // In TX Direct Synchronous mode, the chip controls the transmit data rate by outputting a TX bit clock (GPIO_PIN_CFG=0x10). The host MCU receives the rising edge of the TX clock and responds by outputting one bit for each clock tick; the chip clocks in this new data bit on the subsequent falling edge of the TX clock. All 2-level modulation modes (OOK, 2FSK, 2GFSK) are supported.
                                // In TX Direct Asynchronous mode, the host MCU controls the transmit data rate; the RFIC has no knowledge of the rate of the incoming TX data stream but simply oversamples the data as fast as possible to determine the bit edge transitions. OOK and 2FSK are supported, but 2GFSK is not supported in this mode.
                                // 4(G)FSK is not supported in either TX Direct Synchronous or TX Direct Asynchronous modes
    }unit;
}prop_modem_mod_type_tu;
typedef union 
{
    uint8_t regValue;
    struct 
    {
        /** bit0
         * ...
         * bit7 */
        uint8_t PH_FIELD_SPLIT : 1;
        uint8_t PH_RX_DISABLE  : 1;
        uint8_t _4FSK_EN : 1;
        uint8_t RESERVER  : 1;
        uint8_t MANCH_POL  : 1;
        uint8_t CRC_INVERT : 1;
        uint8_t CRC_ENDIAN : 1;
        uint8_t BIT_ORDER : 1;
    }unit;
}pkt_config1_tu;
//! \brief Structure for the TX Packet
typedef struct
{
    uint8_t rmvAddr[8];              //
    uint32_t absTime;                //
    uint8_t len;                     //
    uint8_t payload[MAX_RF_PACKET_LEN];       //
} rfTxPacket_ts;

typedef struct
{
    uint8_t rmvAddr[8];              //
    int16_t rssi;                     //
    uint32_t absTime;                //
    uint32_t rxTimeout;              //
    uint8_t len;                     //
    uint8_t payload[MAX_RF_PACKET_LEN];
} rfRxPacket_ts;
typedef struct
{
    uint8_t SignalBw;                   // LORA [0: 7.8 kHz, 1: 10.4 kHz, 2: 15.6 kHz, 3: 20.8 kHz, 4: 31.2 kHz,
                                        // 5: 41.6 kHz, 6: 62.5 kHz, 7: 125 kHz, 8: 250 kHz, 9: 500 kHz, other: Reserved]  
    uint8_t SpreadingFactor;            // LORA [6: 64, 7: 128, 8: 256, 9: 512, 10: 1024, 11: 2048, 12: 4096  chips]
    uint8_t ErrorCoding;                // LORA [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
}loraBaudrateFrame_ts;
typedef enum 
{
    RADIO_EXT_CONTROL_TX_UNMODULATED,   //µ¥Ôز¨¹¦ÂʲâÊÔ
    RADIO_EXT_CONTROL_RX_SENSITIVITY,   //½ÓÊÕÁéÃô¶È²âÊÔ
    RADIO_EXT_CONTROL_TX_MODULATED,   //Á¬Ðøµ÷ÖƲâÊÔ
}controlMode_te;
typedef enum
{
    RX_STA_SECCESS,
    RX_STA_TIMEOUT,
    RX_STA_PAYLOAD_ERROR,
    TX_STA_SECCESS,
    TX_STA_ERROR,
}rxStatus_te;
typedef void (*rfRxCallBack)(uint8_t status, rfRxPacket_ts packet);

void myRadio_init(int agr0, void *agr1_ptr);
void myRadio_abort(void);
uint32_t myRadio_getFrequency(void);
void myRadio_setFrequency(uint32_t freq);
int8_t myRadio_getTxPower(void);
void myRadio_setTxPower(int8_t power);
uint32_t myRadio_getBaudrate(void);
void myRadio_setBaudrate(uint32_t br);
void myRadio_setChipType(uint8_t type);
uint8_t myRadio_getChipType(void);
int16_t myRadio_getRssi(void);
void myRadio_transmit(rfTxPacket_ts *packet);
void myRadio_receiver(void);
void myRadio_setCtrl(controlMode_te mode, uint32_t value);

#endif