更新gitignore

.gitignore

@@ -7,6 +7,9 @@ example/MDK/*
 # 但不忽略example/MDK文件夹下的.uvprojx和.uvproj文件  
 !example/MDK/*.uvprojx  
 !example/MDK/*.uvoptx
+!example/MDK/*.s
+!example/MDK/*.sfr
+!example/MDK/*.FLM
 # 忽略my_folder文件夹下的所有文件和文件夹  
 example/EWARM/*  
 # 但不忽略example/EWARM文件夹下的.uvprojx和.uvproj文件  

example/MDK/HC32L130F8UA.uvoptx

@@ -205,7 +205,7 @@
 
   <Group>
     <GroupName>common</GroupName>
-    <tvExp>0</tvExp>
+    <tvExp>1</tvExp>
     <tvExpOptDlg>0</tvExpOptDlg>
     <cbSel>0</cbSel>
     <RteFlg>0</RteFlg>

example/MDK/startup_hc32l130f8ua.s

@@ -0,0 +1,265 @@
+;/******************************************************************************
+; * Copyright (C) 2021, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+; *
+; * This software component is licensed by XHSC under BSD 3-Clause license
+; * (the "License"); You may not use this file except in compliance with the
+; * License. You may obtain a copy of the License at:
+; *                    opensource.org/licenses/BSD-3-Clause
+; *
+; ******************************************************************************/
+
+;/*****************************************************************************/
+;/*  Startup for ARM                                                          */
+;/*  Version     V1.0                                                         */
+;/*  Date        2021-12-02                                                   */
+;/*  Target-mcu  {MCU_PN_H}                                                     */
+;/*****************************************************************************/
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+;  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors                       
+                DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset        
+                DCD     NMI_Handler               ; NMI
+                DCD     HardFault_Handler         ; Hard Fault
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV
+                DCD     SysTick_Handler           ; SysTick
+
+                DCD     PORTA_IRQHandler
+                DCD     PORTB_IRQHandler
+                DCD     PORTC_IRQHandler
+                DCD     PORTD_IRQHandler
+                DCD     DMAC_IRQHandler
+                DCD     TIM3_IRQHandler
+                DCD     UART0_IRQHandler
+                DCD     UART1_IRQHandler
+                DCD     LPUART0_IRQHandler
+                DCD     LPUART1_IRQHandler
+                DCD     SPI0_IRQHandler
+                DCD     SPI1_IRQHandler
+                DCD     I2C0_IRQHandler
+                DCD     I2C1_IRQHandler
+                DCD     TIM0_IRQHandler
+                DCD     TIM1_IRQHandler
+                DCD     TIM2_IRQHandler
+                DCD     LPTIM_IRQHandler
+                DCD     TIM4_IRQHandler
+                DCD     TIM5_IRQHandler
+                DCD     TIM6_IRQHandler
+                DCD     PCA_IRQHandler
+                DCD     WDT_IRQHandler
+                DCD     RTC_IRQHandler
+                DCD     ADC_IRQHandler
+                DCD     PCNT_IRQHandler
+                DCD     VC0_IRQHandler
+                DCD     VC1_IRQHandler
+                DCD     LVD_IRQHandler
+                DCD     LCD_IRQHandler
+                DCD     EF_RAM_IRQHandler
+                DCD     CLKTRIM_IRQHandler
+
+                
+
+__Vectors_End
+
+__Vectors_Size 	EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+
+               ;reset NVIC if in rom debug
+                LDR     R0, =0x20000000
+                LDR     R2, =0x0
+                MOVS    R1, #0                 ; for warning, 
+                ADD     R1, PC,#0              ; for A1609W, 
+                CMP     R1, R0
+                BLS     RAMCODE
+
+              ; ram code base address. 
+                ADD     R2, R0,R2
+RAMCODE
+              ; reset Vector table address.
+                LDR     R0, =0xE000ED08 
+                STR     R2, [R0]
+
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+                
+                
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  PORTA_IRQHandler                [WEAK]
+                EXPORT  PORTB_IRQHandler                [WEAK]
+                EXPORT  PORTC_IRQHandler                [WEAK]
+                EXPORT  PORTD_IRQHandler                [WEAK]
+                EXPORT  DMAC_IRQHandler                 [WEAK]
+                EXPORT  TIM3_IRQHandler                 [WEAK]
+                EXPORT  UART0_IRQHandler                [WEAK]
+                EXPORT  UART1_IRQHandler                [WEAK]
+                EXPORT  LPUART0_IRQHandler              [WEAK]
+                EXPORT  LPUART1_IRQHandler              [WEAK]
+                EXPORT  SPI0_IRQHandler                 [WEAK]
+                EXPORT  SPI1_IRQHandler                 [WEAK]
+                EXPORT  I2C0_IRQHandler                 [WEAK]
+                EXPORT  I2C1_IRQHandler                 [WEAK]
+                EXPORT  TIM0_IRQHandler                 [WEAK]
+                EXPORT  TIM1_IRQHandler                 [WEAK]
+                EXPORT  TIM2_IRQHandler                 [WEAK]
+                EXPORT  LPTIM_IRQHandler                [WEAK]
+                EXPORT  TIM4_IRQHandler                 [WEAK]
+                EXPORT  TIM5_IRQHandler                 [WEAK]
+                EXPORT  TIM6_IRQHandler                 [WEAK]
+                EXPORT  PCA_IRQHandler                  [WEAK]
+                EXPORT  WDT_IRQHandler                  [WEAK]
+                EXPORT  RTC_IRQHandler                  [WEAK]
+                EXPORT  ADC_IRQHandler                  [WEAK]
+                EXPORT  PCNT_IRQHandler                 [WEAK]
+                EXPORT  VC0_IRQHandler                  [WEAK]
+                EXPORT  VC1_IRQHandler                  [WEAK]
+                EXPORT  LVD_IRQHandler                  [WEAK]
+                EXPORT  LCD_IRQHandler                  [WEAK]
+                EXPORT  EF_RAM_IRQHandler               [WEAK]
+                EXPORT  CLKTRIM_IRQHandler              [WEAK]
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+DMAC_IRQHandler
+TIM3_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+LPUART0_IRQHandler
+LPUART1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+TIM0_IRQHandler
+TIM1_IRQHandler
+TIM2_IRQHandler
+LPTIM_IRQHandler
+TIM4_IRQHandler
+TIM5_IRQHandler
+TIM6_IRQHandler
+PCA_IRQHandler
+WDT_IRQHandler
+RTC_IRQHandler
+ADC_IRQHandler
+PCNT_IRQHandler
+VC0_IRQHandler
+VC1_IRQHandler
+LVD_IRQHandler
+LCD_IRQHandler
+EF_RAM_IRQHandler
+CLKTRIM_IRQHandler
+
+                
+               B .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END

example/MDK/startup_hc32l13x.s

@@ -0,0 +1,298 @@
+;/******************************************************************************
+;* Copyright (C) 2019, Xiaohua Semiconductor Co.,Ltd All rights reserved.
+;*
+;* This software is owned and published by:
+;* Xiaohua Semiconductor Co.,Ltd ("XHSC").
+;*
+;* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
+;* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+;*
+;* This software contains source code for use with XHSC
+;* components. This software is licensed by XHSC to be adapted only
+;* for use in systems utilizing XHSC components. XHSC shall not be
+;* responsible for misuse or illegal use of this software for devices not
+;* supported herein. XHSC is providing this software "AS IS" and will
+;* not be responsible for issues arising from incorrect user implementation
+;* of the software.
+;*
+;* Disclaimer:
+;* XHSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+;* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
+;* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
+;* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
+;* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
+;* WARRANTY OF NONINFRINGEMENT.
+;* XHSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
+;* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
+;* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
+;* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
+;* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
+;* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
+;* SAVINGS OR PROFITS,
+;* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+;* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+;* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
+;* FROM, THE SOFTWARE.
+;*
+;* This software may be replicated in part or whole for the licensed use,
+;* with the restriction that this Disclaimer and Copyright notice must be
+;* included with each copy of this software, whether used in part or whole,
+;* at all times.
+;*/
+;/*****************************************************************************/
+
+;/*****************************************************************************/
+;/*  Startup for ARM                                                          */
+;/*  Version     V1.0                                                         */
+;/*  Date        2019-03-01                                                   */
+;/*  Target-mcu  {MCU_PN_H}                                                   */
+;/*****************************************************************************/
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+Stack_Size      EQU     0x00000200
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+;  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors                       
+                DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset        
+                DCD     NMI_Handler               ; NMI
+                DCD     HardFault_Handler         ; Hard Fault
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV
+                DCD     SysTick_Handler           ; SysTick
+
+                DCD     PORTA_IRQHandler
+                DCD     PORTB_IRQHandler
+                DCD     PORTC_IRQHandler
+                DCD     PORTD_IRQHandler
+                DCD     DMAC_IRQHandler
+                DCD     TIM3_IRQHandler
+                DCD     UART0_IRQHandler
+                DCD     UART1_IRQHandler
+                DCD     LPUART0_IRQHandler
+                DCD     LPUART1_IRQHandler
+                DCD     SPI0_IRQHandler
+                DCD     SPI1_IRQHandler
+                DCD     I2C0_IRQHandler
+                DCD     I2C1_IRQHandler
+                DCD     TIM0_IRQHandler
+                DCD     TIM1_IRQHandler
+                DCD     TIM2_IRQHandler
+                DCD     LPTIM_IRQHandler
+                DCD     TIM4_IRQHandler
+                DCD     TIM5_IRQHandler
+                DCD     TIM6_IRQHandler
+                DCD     PCA_IRQHandler
+                DCD     WDT_IRQHandler
+                DCD     RTC_IRQHandler
+                DCD     ADC_IRQHandler
+                DCD     PCNT_IRQHandler
+                DCD     VC0_IRQHandler
+                DCD     VC1_IRQHandler
+                DCD     LVD_IRQHandler
+                DCD     LCD_IRQHandler
+                DCD     FLASH_RAM_IRQHandler
+                DCD     CLKTRIM_IRQHandler
+
+                
+
+__Vectors_End
+
+__Vectors_Size 	EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+
+               ;reset NVIC if in rom debug
+                LDR     R0, =0x20000000
+                LDR     R2, =0x0
+                MOVS    R1, #0                 ; for warning, 
+                ADD     R1, PC,#0              ; for A1609W, 
+                CMP     R1, R0
+                BLS     RAMCODE
+
+              ; ram code base address. 
+                ADD     R2, R0,R2
+RAMCODE
+              ; reset Vector table address.
+                LDR     R0, =0xE000ED08 
+                STR     R2, [R0]
+
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+                
+                
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  PORTA_IRQHandler                [WEAK]
+                EXPORT  PORTB_IRQHandler                [WEAK]
+                EXPORT  PORTC_IRQHandler                [WEAK]
+                EXPORT  PORTD_IRQHandler                [WEAK]
+                EXPORT  DMAC_IRQHandler                 [WEAK]
+                EXPORT  TIM3_IRQHandler                 [WEAK]
+                EXPORT  UART0_IRQHandler                [WEAK]
+                EXPORT  UART1_IRQHandler                [WEAK]
+                EXPORT  LPUART0_IRQHandler              [WEAK]
+                EXPORT  LPUART1_IRQHandler              [WEAK]
+                EXPORT  SPI0_IRQHandler                 [WEAK]
+                EXPORT  SPI1_IRQHandler                 [WEAK]
+                EXPORT  I2C0_IRQHandler                 [WEAK]
+                EXPORT  I2C1_IRQHandler                 [WEAK]
+                EXPORT  TIM0_IRQHandler                 [WEAK]
+                EXPORT  TIM1_IRQHandler                 [WEAK]
+                EXPORT  TIM2_IRQHandler                 [WEAK]
+                EXPORT  LPTIM_IRQHandler                [WEAK]
+                EXPORT  TIM4_IRQHandler                 [WEAK]
+                EXPORT  TIM5_IRQHandler                 [WEAK]
+                EXPORT  TIM6_IRQHandler                 [WEAK]
+                EXPORT  PCA_IRQHandler                  [WEAK]
+                EXPORT  WDT_IRQHandler                  [WEAK]
+                EXPORT  RTC_IRQHandler                  [WEAK]
+                EXPORT  ADC_IRQHandler                  [WEAK]
+                EXPORT  PCNT_IRQHandler                 [WEAK]
+                EXPORT  VC0_IRQHandler                  [WEAK]
+                EXPORT  VC1_IRQHandler                  [WEAK]
+                EXPORT  LVD_IRQHandler                  [WEAK]
+                EXPORT  LCD_IRQHandler                  [WEAK]
+                EXPORT  FLASH_RAM_IRQHandler            [WEAK]
+                EXPORT  CLKTRIM_IRQHandler              [WEAK]
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+DMAC_IRQHandler
+TIM3_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+LPUART0_IRQHandler
+LPUART1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+TIM0_IRQHandler
+TIM1_IRQHandler
+TIM2_IRQHandler
+LPTIM_IRQHandler
+TIM4_IRQHandler
+TIM5_IRQHandler
+TIM6_IRQHandler
+PCA_IRQHandler
+WDT_IRQHandler
+RTC_IRQHandler
+ADC_IRQHandler
+PCNT_IRQHandler
+VC0_IRQHandler
+VC1_IRQHandler
+LVD_IRQHandler
+LCD_IRQHandler
+FLASH_RAM_IRQHandler
+CLKTRIM_IRQHandler
+
+                
+               B .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END